Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: nb/x4x/raminit.c: Remove ME locking code

Browse source 
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.

Intel  4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2515e965aafbac95e78eef9a42ce10c302c892d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddc8828697
Original-Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18513
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/501147
This commit is contained in:
Arthur Heymans 2017-02-27 16:27:21 +01:00 • committed by chrome-bot
parent 6434755b96
commit 4adf1480ee
1 changed files with 12 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/northbridge/intel/x4x/raminit_ddr2.c
View file

@ -2106,15 +2106,19 @@ void raminit_ddr2(struct sysinfo *s)
printk(BIOS_DEBUG, "Done power settings\n");
// ME related
/*
* FIXME: This locks some registers like bit1 of GGC
* and is only needed in case of ME being used.
*/
if (ME_UMA_SIZEMB != 0) {
if (RANK_IS_POPULATED(s->dimms, 0, 0)
|| RANK_IS_POPULATED(s->dimms, 1, 0)) {
|| RANK_IS_POPULATED(s->dimms, 1, 0))
MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0);
}
if (RANK_IS_POPULATED(s->dimms, 0, 1)
|| RANK_IS_POPULATED(s->dimms, 1, 1)) {
|| RANK_IS_POPULATED(s->dimms, 1, 1))
MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1);
}
MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26);
}
printk(BIOS_DEBUG, "Done ddr2\n");
}