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rockchip: spi: Improve SPI read efficiency

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The SPI driver is quite slow at reading data. For example, with a 24MHz
clock on gru it achieves a read speed of only 13.9Mbps.

We can correct this by reading the status registers once, then reading as
many bytes as are available before checking the status registers again. It
seems likely that a status register read requires synchronizing with the
SPI FIFO clock domain, which takes a while.

BUG=chrome-os-partner:56556
BRANCH=none
TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps

Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376945
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Simon Glass 2016-08-27 15:10:30 -06:00 • committed by chrome-bot
parent 4e7a42c999
commit 49c2fc20d7
2 changed files with 18 additions and 4 deletions
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7
src/soc/rockchip/common/include/soc/spi.h
View file

@ -165,6 +165,13 @@ check_member(rockchip_spi, rxdr, 0x800);
#define SPI_OMOD_SLAVE 0x01
/* --------Bit fields in CTRLR0--------end */
/* TXFLR bits */
#define TXFLR_LEVEL_MASK 0x3f
/* RXFLR bits */
#define RXFLR_LEVEL_MASK 0x3f
/* Bit fields in SR, 7 bits */
#define SR_MASK 0x7f
#define SR_BUSY (1 << 0)

15
src/soc/rockchip/common/spi.c
View file

@ -235,11 +235,18 @@ static int do_xfer(struct rockchip_spi *regs, const void *dout,
xferred = 1;
}
/*
* Try to read as many bytes as are available in one go.
* Reading the status registers probably requires
* sychronizing with the SPI clock which is pretty slow.
*/
if (*bytes_in && !(sr & SR_RF_EMPT)) {
*in_buf = read32(&regs->rxdr) & 0xff;
in_buf++;
*bytes_in -= 1;
xferred = 1;
int todo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK;
*bytes_in -= todo;
xferred = todo;
while (todo-- > 0)
*in_buf++ = read32(&regs->rxdr) & 0xff;
}
min_xfer -= xferred;