mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Fixed the device on bus 0 problem for IBM/E325. The structure mainboard_ibm_e325_control is
not actually defined in the mainboard.c. It was only declared in chip.h. Why gcc did not tell me this mistake and why gcc does not complain about define a structure twice ? git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
5782d273eb
commit
48d11d557f
4 changed files with 36 additions and 9 deletions
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@ -30,7 +30,7 @@ static void hard_reset(void)
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set_bios_reset();
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set_bios_reset();
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/* enable cf9 */
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/* enable cf9 */
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pci_write_config8(PCI_DEV(1, 0x04, 3), 0x41, 0xf1);
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pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
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/* reset */
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/* reset */
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outb(0x0e, 0x0cf9);
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outb(0x0e, 0x0cf9);
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}
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}
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@ -38,7 +38,7 @@ static void hard_reset(void)
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static void soft_reset(void)
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static void soft_reset(void)
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{
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{
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set_bios_reset();
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set_bios_reset();
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pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
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pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
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}
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}
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static void memreset_setup(void)
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static void memreset_setup(void)
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@ -171,18 +171,37 @@ static void main(void)
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pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
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pc87366_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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uart_init();
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console_init();
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console_init();
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#if 0
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print_pci_devices();
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#endif
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setup_ibm_e325_resource_map();
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setup_ibm_e325_resource_map();
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#if 0
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print_debug("after setting resource\n");
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print_pci_devices();
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#endif
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needs_reset = setup_coherent_ht_domain();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
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#if 0
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print_debug("after ht stuff\n");
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print_pci_devices();
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#endif
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if (needs_reset) {
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if (needs_reset) {
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print_info("ht reset -\r\n");
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print_info("ht reset -\r\n");
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soft_reset();
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soft_reset();
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}
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}
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#if 1
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#if 0
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print_pci_devices();
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print_pci_devices();
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#endif
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#endif
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enable_smbus();
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enable_smbus();
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#if 0
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#if 0
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dump_spd_registers(&cpu[0]);
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dump_spd_registers(&cpu[0]);
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#endif
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#endif
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@ -193,6 +212,7 @@ static void main(void)
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#if 0
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#if 0
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dump_pci_devices();
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dump_pci_devices();
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#endif
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#endif
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#if 0
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#if 0
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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#endif
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@ -279,7 +279,7 @@ static void enumerate(struct chip *chip)
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child->bus = &dev_root.link[0];
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child->bus = &dev_root.link[0];
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}
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}
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}
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}
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struct chip_control mainboard_arima_hdama_control = {
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struct chip_control mainboard_ibm_e325_control = {
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.enumerate = enumerate,
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.enumerate = enumerate,
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.name = "IBM E325 mainboard ",
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.name = "IBM E325 mainboard ",
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};
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};
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@ -260,10 +260,10 @@ static void setup_ibm_e325_resource_map(void)
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* [31:24] Bus Number Limit i
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration regin i
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* This field defines the highest bus number in configuration regin i
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*/
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*/
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PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0xff000103,
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PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0xff040103,
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PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0,
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PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0,
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};
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};
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int max;
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int max;
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max = sizeof(register_values)/sizeof(register_values[0]);
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max = sizeof(register_values)/sizeof(register_values[0]);
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@ -488,11 +488,19 @@ static void amdk8_set_resources(device_t dev)
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unsigned int amdk8_scan_root_bus(device_t root, unsigned int max)
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unsigned int amdk8_scan_root_bus(device_t root, unsigned int max)
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{
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{
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unsigned reg;
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unsigned reg;
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printk_debug("amdk8_scan_root_bus\n");
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/* Unmap all of the HT chains */
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/* Unmap all of the HT chains */
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for (reg = 0xe0; reg <= 0xec; reg += 4) {
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for (reg = 0xe0; reg <= 0xec; reg += 4) {
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printk_debug("amdk8_scan_root: clearing register %x\n", reg);
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f1_write_config32(reg, 0);
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f1_write_config32(reg, 0);
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}
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}
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printk_debug("amdk8_scan_root_bus: start scan pci bus\n");
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max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
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max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
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printk_debug("amdk8_scan_root_bus: done\n");
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return max;
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return max;
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}
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}
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@ -529,12 +537,11 @@ static void amdk8_enable_resources(struct device *dev)
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ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
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ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
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ctrl |= dev->link[0].bridge_ctrl;
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ctrl |= dev->link[0].bridge_ctrl;
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printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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printk_err("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
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#if 0
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#if 0
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/* let's see what link VGA is on */
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/* let's see what link VGA is on */
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for(link = 0; link < dev->links; link++) {
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for (link = 0; link < dev->links; link++) {
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device_t child;
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device_t child;
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printk_err("Kid %d of k8: bridge ctrl says: 0x%x\n",
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printk_err("Kid %d of k8: bridge ctrl says: 0x%x\n",
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link, dev->link[link].bridge_ctrl);
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link, dev->link[link].bridge_ctrl);
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