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https://github.com/fail0verflow/switch-coreboot.git
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support for ga-6bxc
This commit is contained in:
Ronald G. Minnich
parent
620dff9ebb
commit
489a632b67
2 changed files with 197 additions and 0 deletions
16
src/mainboard/intel/l440gx/BUILD_PHLASH_FILES
Normal file
16
src/mainboard/intel/l440gx/BUILD_PHLASH_FILES
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@ -0,0 +1,16 @@
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#!/bin/sh
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phlash=$1
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if [ "$phlash" = "" ] ; then
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phlash=p11-0102
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fi
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dd bs=65696 conv=sync of=/tmp/$phlash.bi1 if=$phlash.bi1
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dd bs=65696 conv=sync of=/tmp/$phlash.bio if=$phlash.bio
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dd bs=65696 conv=sync of=/tmp/$phlash.bi3 if=$phlash.bi3
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dd bs=65696 conv=sync of=/tmp/$phlash.bi2 if=$phlash.bi2
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dd bs=65696 conv=sync of=/tmp/$phlash.bi5 if=$phlash.bi5
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dd bs=65696 conv=sync of=/tmp/$phlash.bi4 if=$phlash.bi4
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dd bs=65696 conv=sync of=/tmp/$phlash.bi7 if=$phlash.bi7
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dd bs=65696 conv=sync of=/tmp/$phlash.bi6 if=$phlash.bi6
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dd bs=65696 conv=sync of=/tmp/$phlash.bi9 if=$phlash.bi9
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dd bs=65696 conv=sync of=/tmp/$phlash.bi8 if=$phlash.bi8
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dd bs=65696 conv=sync of=/tmp/$phlash.bia if=$phlash.bia
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181
src/northbridge/intel/440bx/raminit.inc
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181
src/northbridge/intel/440bx/raminit.inc
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// TODO: take out GA-6BXC references
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#if 0
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/* CAS latency 2 */
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#define CAS_NB 0x17
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#define CAS_RAM 0x150
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#elif 1
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/* CAS latency 3 */
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#define CAS_NB 0x03
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#define CAS_RAM 0x1d0
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#endif
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/* 1 or 2 dimms */
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#ifdef GA6BXC_256M
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#define DRB 0x20
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#define DIMM2_READ2 mov 0x08002000, %eax
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#define DIMM2_READ mov 0x08000000, %eax
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#define DIMM2_MRS mov 0x08000000+CAS_RAM, %eax
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#define RPS 0x22
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#define PGPOL 0x26
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#define MBSC 0x01
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#define DRB2 0x10
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#define RPS2 0x02
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#define PGPOL2 0x23
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#define MBSC2 0x00
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#else
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#define DRB 0x10
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#define DIMM2_READ2
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#define DIMM2_READ
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#define DIMM2_MRS
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#define RPS 0x02
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#define PGPOL 0x23
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#define MBSC 0x00
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#endif
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/* this sets up the intel 440BX SDRAM. */
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invd
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mov %cr0, %eax
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or $0x60000000, %eax // cache disable bits on
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mov %eax, %cr0
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CS_WRITE($0x77, $0x01) /* SDRAMC */
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CS_WRITE($0x57, $0x08) /* DRAMC */
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/* PAM - Programmable Attribute Map Registers */
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CS_WRITE($0x59, $0)
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CS_WRITE($0x5a, $0)
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CS_WRITE($0x5b, $0)
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CS_WRITE($0x5c, $0)
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CS_WRITE($0x5d, $0)
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CS_WRITE($0x5e, $0)
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CS_WRITE($0x5f, $0)
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/* DRB - DRAM Row Boundry Registers */
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CS_WRITE($0x60, $0x10) /* 128 MB on slot 0 front */
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CS_WRITE($0x61, $0x10) /* 0 MB on slot 0 back */
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CS_WRITE($0x62, $DRB ) /* 128 MB on slot 1 front */
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CS_WRITE($0x63, $DRB ) /* 0 MB on slot 1 back */
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CS_WRITE($0x64, $DRB ) /* 0 MB on slot 2 front */
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CS_WRITE($0x65, $DRB ) /* 0 MB on slot 2 back */
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CS_WRITE($0x66, $DRB ) /* 0 MB on slot 3 front */
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CS_WRITE($0x67, $DRB ) /* 0 MB on slot 3 back */
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/* MBSC - Memory buffer strength control */
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CS_WRITE($0x69, $0x00)
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CS_WRITE($0x6a, $0x40)
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CS_WRITE($0x6b, $MBSC)
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CS_WRITE($0x6c, $0x00)
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CS_WRITE($0x6d, $0x8a)
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CS_WRITE($0x6e, $0x00)
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/* RPS - Row Page Size Register */
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CS_WRITE($0x74, $RPS)
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CS_WRITE($0x75, $0x00)
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/* PGPOL - Paging Policy Register */
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CS_WRITE($0x78, $PGPOL)
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CS_WRITE($0x79, $0xff)
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/* MBFS - Memory Buffer Frequency Select Register */
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CS_WRITE($0xca, $0xff)
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CS_WRITE($0xcb, $0xff)
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CS_WRITE($0xcc, $0x61)
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/* NOP */
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CS_WRITE($0x76, $0x20+CAS_NB) /* SDRAMC */
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mov 0x00000000, %eax
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DIMM2_READ
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/* delay 200 us (100us/loop) */
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mov $2, %ecx
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1:
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nop
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loop 1b
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/* Precharge all */
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CS_WRITE($0x76, $0x40+CAS_NB)
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mov 0x00002000, %eax
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DIMM2_READ2
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/* eight CBRs */
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CS_WRITE($0x76, $0x80+CAS_NB)
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/* delay at least 100 ns between reads. (ISA access/no cache, slow) */
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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mov 0x00000000, %eax
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DIMM2_READ
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/* mode register set*/
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CS_WRITE($0x76, $0x60+CAS_NB)
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mov 0x00000000+CAS_RAM, %eax
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DIMM2_MRS
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/* normal operation */
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CS_WRITE($0x76, $0x00+CAS_NB)
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CS_WRITE($0x57, $0x09) /* DRAMC */
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#ifdef GA6BXC_256M
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mov $0x40, %ecx
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mov $0x8000000, %ebx
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1:
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mov %ebx, (%ebx)
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add $4, %ebx
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loop 1b
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mov $0x40, %ecx
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mov $0x8000000, %ebx
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1:
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cmp %ebx, (%ebx)
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jne 1f
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add $4, %ebx
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loop 1b
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jmp 2f
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1:
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CS_WRITE($0x62, $DRB2 ) /* 0 MB on slot 1 front */
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CS_WRITE($0x63, $DRB2 ) /* 0 MB on slot 1 back */
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CS_WRITE($0x64, $DRB2 ) /* 0 MB on slot 2 front */
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CS_WRITE($0x65, $DRB2 ) /* 0 MB on slot 2 back */
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CS_WRITE($0x66, $DRB2 ) /* 0 MB on slot 3 front */
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CS_WRITE($0x67, $DRB2 ) /* 0 MB on slot 3 back */
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CS_WRITE($0x6b, $MBSC2)
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CS_WRITE($0x74, $RPS2)
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CS_WRITE($0x78, $PGPOL2)
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2:
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#endif
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