From 48607dd0b732c7ccd9683b78f7b667a39b5bfe50 Mon Sep 17 00:00:00 2001
From: "Ronald G. Minnich" <rminnich@gmail.com>
Date: Wed, 29 Nov 2000 19:46:39 +0000
Subject: [PATCH] L2 cache code is solid. Experimenting with VIA SPD code -- no
 good.

---
 romimages/RON_VIA_SPD/crt0.S |  2 +-
 src/cpu/p6/l2_cache.c        | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/romimages/RON_VIA_SPD/crt0.S b/romimages/RON_VIA_SPD/crt0.S
index eed413e0e8..52315035d6 100644
--- a/romimages/RON_VIA_SPD/crt0.S
+++ b/romimages/RON_VIA_SPD/crt0.S
@@ -29,8 +29,8 @@
 #include <southbridge/via/vt82c686/setup_serial.inc>
 
 #include <pc80/serial.inc>
-/*
 #include <pc80/i8259.inc>
+/*
  */
 
 	TTYS0_TX_STRING($ttyS0_test)
diff --git a/src/cpu/p6/l2_cache.c b/src/cpu/p6/l2_cache.c
index 5a1c3b22b2..87ba086a6a 100644
--- a/src/cpu/p6/l2_cache.c
+++ b/src/cpu/p6/l2_cache.c
@@ -70,7 +70,8 @@ static void cache_disable(void)
 		      "orl  $0x40000000, %0\n\t"
 		      "wbinvd\n\t"
 		      "movl  %0, %%cr0\n\t"
-		      "wbinvd\n\t":"=r" (tmp)::"memory");
+		      "wbinvd\n\t"
+		      : "=r" (tmp) : : "memory");
 }
 
 static void cache_enable(void)
@@ -79,7 +80,8 @@ static void cache_enable(void)
 
 	asm volatile ("movl  %%cr0, %0\n\t"
 		      "andl  $0x9fffffff, %0\n\t"
-		      "movl  %0, %%cr0\n\t":"=r" (tmp)::"memory");
+		      "movl  %0, %%cr0\n\t"
+		      :"=r" (tmp) : : "memory");
 }
 
 int intel_l2_configure()
@@ -107,8 +109,7 @@ int intel_l2_configure()
 	}
 
 	if (signature < 0x630 || signature >= 0x680) {
-		DBG
-		    ("CPU signature of %x so no need for L2 cache configuration\n",
+		DBG("CPU signature of %x so no L2 cache configuration\n",
 		     signature);
 		return 0;
 	}
@@ -404,7 +405,7 @@ static int write_l2_2(unsigned int address,
 	data2 &= 0x1800;
 	data1 |= data2;
 
-	data2 = data2 >> 6;
+	data2 = data2 << 6;
 	data2 &= 0x20000;
 	data1 |= data2;