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intel/skylake: Add gpio macro for unused GPIO pins

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Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.

BUG=none
BRANCH=none
TEST=Build and boot lars

Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319964
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/13628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
david 2015-12-29 15:02:04 +08:00 • committed by Martin Roth
parent 1c85fea945
commit 4852dec1ab
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/skylake/include/soc/gpio.h
View file

@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_PAD_CFG(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO))
/* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled. */
#define PAD_CFG_NC(pad_) \
_PAD_CFG(pad_, NONE, \
_DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES))
/* General purpose output with termination. */
#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
_PAD_CFG(pad_, term_, \