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Drop obsolete files from doc/design.

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@251 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-03-12 10:34:56 +00:00
parent d2b58cdd6f
commit 4739d0078d
3 changed files with 0 additions and 352 deletions
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57
doc/design/dtsk8
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@ -1,57 +0,0 @@
/{
model = "qemu";
#address-cells = <1>;
#size-cells = <1>;
compatible = "emulation-i386,qemu";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu,emulation,qemu-i386@0{
device_type = "cpu";
clock-frequency = <5f5e1000>;
timebase-frequency = <1FCA055>;
linux,boot-cpu;
reg = <0>;
i-cache-size = <2000>;
d-cache-size = <2000>;
links=<&northbridge,intel,440bx &/northbridge,intel,440bx>;
};
};
spd = <
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
>;
memory@0 {
device_type = "memory";
reg = <00000000 20000000>;
};
/* the I/O stuff */
northbridge,intel,440bx{
southbridge,intel,piix4{
superio,nsc,sucks{
uart@0{
enabled=<1>;
};
};
};
};
chosen {
bootargs = "root=/dev/sda2";
linux,platform = <00000600>;
linux,stdout-path="/dev/ttyS0";
};
options {
normal="normal";
fallback="fallback";
};
};

155
doc/design/stage1.c
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@ -1,155 +0,0 @@
/* the standard LinuxBIOS include file has constant definitions, types and so on */
#include <linuxbios.h>
#if 0
/* NOTES */
/* support library code. */
src/LinuxBIOSv2/src/cpu/x86/lapic/boot_cpu.c -- which cpu is the boot cpu
src/LinuxBIOSv2/src/northbridge/amd/amdk8/reset_test.c -- determine if we had a reset -- hard or soft
src/LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c -- early mtrr setup
/* this is currently used but may be replaced by properties for the CPUs */
northbridge/amd/amdk8/setup_resource_map.c -- map of 18.1 device for routing
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#endif
/* there is a global struct used by main, that is the dtb tree */
/* it is built when the LinuxBIOS image is built */
/* it is linked in, as it is generated as a C struct */
extern struct dtb *dtb;
/* basic ugly crud that is not at all elegant ... very mainboard specific, has to be done this way */
static void stage1_superio_setup(void)
{
struct property *superio;
unsigned value;
u32 dword;
u8 byte;
superio = get_property(dtb, "ck804");
/* read dev 1 , function 0, of the superio, */
byte = pci_read_config8(superio, 1, 0, 0x7b);
byte |= 0x20;
pci_write_config8(superio, 1, 0, 0x7b, byte);
dword = pci_read_config32(superio, 1, 0, 0xa0);
dword |= (1<<0);
pci_write_config32(superio, 1, 0, 0xa0, dword);
}
/* assumptions: when we get here, we have a small region of cache-as-ram usable as a stack.
* we have the DTB in flash. bist (built-in-self-test) and cpu_init_detectedx are set by CAR code.
* This code is common to both fallback and normal images, so we do it in pre_initram support.
*/
/* what we have to do:
* enable console(s)
* make the processors sane
* do initial hardware enable
*/
void stage1(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct property *image;
struct property *uart;
struct LAR_dir *dir;
struct LAR_file *file;
struct LAR_file *decompressor;
void (*code)():
int needs_reset;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
unsigned nodes;
unsigned last_boot_normal_x = last_boot_normal(); /* from CMOS */
/* Is this a cpu only reset? or Is this a secondary cpu? */
/* cpu only means we came here before, set up some basic things (e.g. hypertransport),
* and found that as part of that we had to reset the CPU to get the bus set up correctly.
* Secondary CPUs do less work than primary CPUs (on K8) and hence do not need to
* do some of the more primitive setup operations (such as setting up routing tables)
*/
if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) {
image = get_property(dtb, "normal");
} else {
image = get_property(dtb, "fallback");
}
} else {
/* we are here because we need to set up baseline hardware after a full reset or power cycle */
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* note that this will be filling in the DTB! */
stage1_enumerate_ht_chain();
uart = get_property(dtb, "uart");
stage1_sio_setup(uart);
/* Setup the ck804 */
stage1_ck804_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) {
image = get_property(dtb, "normal");
}
/* This is the primary cpu; is this a normal or fallback boot? Determined mostly by CMOS settings */
else if (do_normal_boot()) {
image = get_property(dtb, "normal");
} else {
image = get_property(dtb, "fallback");
}
}
/* now, using the image property as a directory name, make the LAR calls to run files in the
* directory. Uncompress as needed. Names are as in the LInux dentry cache, pointer + length
*/
dir = LAR_lookup(image->val.val, image->val.len);
dir = LAR_walk(dir, "stage2");
/* LAR_walk walks from a directory to another directory or file */
file = LAR_walk(dir, "initram");
if (! file) {
/*uh oh!*/
}
/* initram is uncompressed. */
code = code_pointer(file);
/* we have to chain to the rest of LinuxBIOS, since CAR will go away */
/* The stack will be gone. Pass two parameters to the initram:
* pointer to function to run when initram is done, and property for booting.
*/
(*code)(stage1_run_stage2, image);
}
void
stage1_run_stage2(struct property *image){
struct property *uart;
struct LAR_dir *dir;
struct LAR_file *file = NULL;
struct LAR_file *decompressor;
void (*code)();
dir = LAR_lookup(image->val.val, image->val.len);
dir = LAR_walk(dir, "stage2");
/* LAR_next just walks to the next file from the current one */
while (file = LAR_next(dir, file)) {
if (! strcmp(file->name, "initram"))
continue;
decompressor = find_decompressor(file);
/* if the decompressor is null, then the function
* just returns a pointer to the start of the file in FLASH
*/
code = run_decompressor(file, decompressor);
if (! code) {
/* it's a bad day! */
}
(*code)();
}
/* NOTREACHED -- last file runs the payload */
}

140
doc/design/stage2.c
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/* the standard LinuxBIOS include file has constant definitions, types and so on */
#include <linuxbios.h>
/* support library code. */
src/LinuxBIOSv2/src/cpu/x86/lapic/boot_cpu.c -- which cpu is the boot cpu
src/LinuxBIOSv2/src/northbridge/amd/amdk8/reset_test.c -- determine if we had a reset -- hard or soft
src/LinuxBIOSv2/src/cpu/amd/mtrr/amd_earlymtrr.c -- early mtrr setup
/* this is currently used but may be replaced by properties for the CPUs */
northbridge/amd/amdk8/setup_resource_map.c -- map of 18.1 device for routing
#define CK804_NUM 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
/* there is a global struct used by main, that is the dtb tree */
/* it is built when the LinuxBIOS image is built */
/* it is linked in, as it is generated as a C struct */
extern struct dtb *dtb;
/* assumptions: when we get here, we have a small region of cache-as-ram usable as a stack.
* we have the DTB in flash. bist (built-in-self-test) and cpu_init_detectedx are set by CAR code.
*/
/* what we have to do:
* enable console(s)
* make the processors sane
* figure out what memory is there and turn it on
* do initial hardware enable
*/
void main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct property *spd;
int spdsize;
struct property *uart;
u16 *spd_addr;
struct property *image;
struct property *uart;
int needs_reset;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
unsigned nodes;
unsigned last_boot_normal_x = last_boot_normal(); /* from CMOS */
/* fill in the SPD entries from the properties.
* the SPD properties are an array of shorts
*/
spd = get_property(dtb, "spd");
if (! spd) /* now what? */
fatal("no SPD properties");
spdsize = spd->val.len / sizeof(uint16);
spd_addr = malloc(spdsize * sizeof(*spd_addr));
for(I = 0; i < spdsize; i++)
spd_addr[i] = be16_to_cpu(*((u32 *)(d.val+i))));
/* we now have the spd addresses from the DTB */
/* There are several ways we could be here. We could be power-on reset,
* in which case we have to init a lot of things. We could be cpu-only reset,
* in which case we just have to clean up the cpu. We could be the
* Attached Processor (AP), in which case it is a lot like a cpu-only reset,
* since a lot of the setup has been done by the Boot Strap Processor (BSP or BP)
*/
if (bist == 0) {
init_cpus(cpu_init_detectedx);
}
uart = get_property(dtb, "uart");
w83627hf_enable_serial(uart);
uart_init(uart);
console_init(uart);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2892_resource_map(dtb);
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain(dtb);
wait_all_core0_started(dtb);
/* this should be determined from dtb. */
numcpus = get_value(dtb, "#cpus");
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
needs_reset |= ht_setup_chains_x(dtb);
needs_reset |= ck804_early_setup_x(dtb);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(dtb);
//It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus(dtb);
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup(dtb);
sdram_initialize(dtb, nodes, ctrl);
#if 0
print_pci_devices();
#endif
#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}