Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: board/intel/amenia: Enable LPSS S0ix

Browse source 
This setting will enable S0ix for LPSS

BUG=None
BRANCH=None
TEST=None

Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/15056
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358833
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Hannah Williams 2016-06-02 15:00:36 -07:00 • committed by chrome-bot
parent 04ebdf4e4e
commit 46f5ad8c3a
1 changed files with 3 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/mainboard/intel/amenia/devicetree.cb
View file

@ -15,6 +15,9 @@ chip soc/intel/apollolake
# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
# LPSS S0ix Enable
register "lpss_s0ix_enable" = "1"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF