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UPSTREAM: google/scarlet: Enable innolux,p079zca MIPI panel

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TEST=Boot from scarlet, and mipi panel works

Change-Id: I28ae05e1d3681a6012da80cf2e2dae196110559c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 36b09b8a6c
Original-Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748
Original-Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Original-Reviewed-on: https://review.coreboot.org/19700
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/508774
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Nickey Yang 2017-05-16 10:40:49 +08:00 • committed by chrome-bot
parent 1f93934c57
commit 4635de1b7f
1 changed files with 13 additions and 1 deletions
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14
src/mainboard/google/gru/devicetree.scarlet.cb
View file

@ -15,6 +15,18 @@
chip soc/rockchip/rk3399
device cpu_cluster 0 on end
register "vop_mode" = "VOP_MODE_NONE"
register "vop_mode" = "VOP_MODE_MIPI"
register "framebuffer_bits_per_pixel" = "32"
register "panel_pixel_clock" = "56900"
register "panel_refresh" = "60"
register "panel_ha" = "768"
register "panel_hbl" = "120"
register "panel_hso" = "40"
register "panel_hspw" = "40"
register "panel_va" = "1024"
register "panel_vbl" = "44"
register "panel_vso" = "20"
register "panel_vspw" = "4"
register "panel_display_on_mdelay" = "120"
register "panel_video_mode_mdelay" = "5"
end