mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
sb/intel/i82801jx: Store initial timestamp in bootblock
The function to fetch this timestamp is already present. Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
parent
f1c8ede1a5
commit
46234ea36b
1 changed files with 14 additions and 0 deletions
|
@ -14,8 +14,21 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
|
#include <cpu/x86/tsc.h>
|
||||||
#include "i82801jx.h"
|
#include "i82801jx.h"
|
||||||
|
|
||||||
|
static void store_initial_timestamp(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* We have two 32bit scratchpad registers available:
|
||||||
|
* D0:F0 0xdc (SKPAD)
|
||||||
|
* D31:F2 0xd0 (SATA SP)
|
||||||
|
*/
|
||||||
|
tsc_t tsc = rdtsc();
|
||||||
|
pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
|
||||||
|
pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
|
||||||
|
}
|
||||||
|
|
||||||
static void enable_spi_prefetch(void)
|
static void enable_spi_prefetch(void)
|
||||||
{
|
{
|
||||||
u8 reg8;
|
u8 reg8;
|
||||||
|
@ -31,6 +44,7 @@ static void enable_spi_prefetch(void)
|
||||||
|
|
||||||
static void bootblock_southbridge_init(void)
|
static void bootblock_southbridge_init(void)
|
||||||
{
|
{
|
||||||
|
store_initial_timestamp();
|
||||||
enable_spi_prefetch();
|
enable_spi_prefetch();
|
||||||
|
|
||||||
/* Enable RCBA */
|
/* Enable RCBA */
|
||||||
|
|
Loading…
Add table
Reference in a new issue