diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f02f9561e2..56cfdee099 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -45,6 +45,7 @@ romstage-y += pei_data.c
 romstage-y += pmutil.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
 romstage-y += smbus_common.c
+romstage-y += early_smbus.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 
diff --git a/src/soc/intel/skylake/early_smbus.c b/src/soc/intel/skylake/early_smbus.c
new file mode 100644
index 0000000000..6df971a35b
--- /dev/null
+++ b/src/soc/intel/skylake/early_smbus.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/smbus_def.h>
+#include <device/early_smbus.h>
+#include <soc/smbus.h>
+#include <soc/iomap.h>
+
+u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
+{
+	return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset);
+}
+
+u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
+{
+	return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
+}