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almost-working changes for sizing remaining dram in c
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1 changed files with 124 additions and 0 deletions
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@ -4,6 +4,130 @@
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// FIX ME!
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// FIX ME!
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unsigned long sizeram()
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unsigned long sizeram()
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{
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{
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extern void cache_disable(void), cache_enable(void);
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int i;
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struct pci_dev *pcidev;
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volatile unsigned char *cp;
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u32 ram;
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unsigned long size;
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pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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if (! pcidev)
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return 0;
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printk("Acer sizeram pcidev %p\n", pcidev);
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/* now read and print registers for ram ...*/
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for(i = 0x6c; i < 0x78; i++) {
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pci_read_config_dword(pcidev, i, &ram);
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size = (1 << (((ram >> 20) & 0x7))) * (0x400000);
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printk("0x%x 0x%x, size 0x%x\n", i, ram, size);
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}
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printk("so is the first one double-sided? \n");
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cache_disable();
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pci_read_config_dword(pcidev, 0x6c, &ram);
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size = (1 << (((ram >> 20) & 0x7))) * (0x400000);
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printk("set cp to 0x%x\n", size);
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cp = (char *) size;
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printk("cp is now %p\n", cp);
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*cp = 0x55;
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// how odd.
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// what happens is if there is a 2nd row, then it will
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// read back REGARDLESS of the settings of the bits in the
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// register! We verified this with the arium ...
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// RGM 4/10/01
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if (*cp == 0x55) {
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ram |= 0x1800000;
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printk("Jam 0x%x into 0x6c\n", ram);
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pci_write_config_dword(pcidev, 0x6c, ram);
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printk("@ cp now is 0x%x\n", *cp);
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// set the base address for the next dram slot
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// (if there is any ... )
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cp += size;
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}
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printk("cp now is 0x%x\n", cp);
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// now do the other two banks.
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#define INIT_MCR 0xf663f83c
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for(i = 0x70; i < 0x78; i += 4) {
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u32 temp;
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unsigned long size, cas, offset;
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printk("OK, let's try the other two banks\n");
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pci_read_config_dword(pcidev, i, &temp);
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pci_write_config_dword(pcidev, i, INIT_MCR);
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printk("Slot 0x%x: set to 0x%x\n", i, INIT_MCR);
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// anyone home?
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printk("Slot 0x%x: set value at %p\n", i, cp);
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*cp = 0x55;
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printk("Slot 0x%x: value at %p is 0x%x\n", cp, *cp);
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if (*cp != 0x55) {
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printk("Nothing in slot 0x%x\n", i);
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pci_write_config_dword(pcidev, i, temp);
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continue;
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}
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// get the cas bank size.
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for(cas = 0, offset = 0x800; ;cas++, offset <<= 1) {
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*cp = 0;
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printk("Slot %x: check at %p\n", i, (cp+offset));
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*(cp + offset) = cas + 1;
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printk("Slot %x: cas %d, *cp %d\n", i, cas, *cp);
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if (*cp)
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break;
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if (cas > 2)
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break;
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}
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printk("Slot 0x%x: cas is 0x%x\n", i, cas);
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// now set the cas value into bits 19:16
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cas <<= 16;
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pci_read_config_dword(pcidev, i, &temp);
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temp &= ~0xf0000;
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temp |= cas;
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pci_write_config_dword(pcidev, i, temp);
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// now size it.
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for(*cp = 0, offset = 0x400000, size = 0;
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size < 7; offset <<= 1, size++) {
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*(cp + offset) = 4;
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if (*cp)
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break;
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}
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printk("Slot 0x%x: size 0x%x\n", i, size);
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// fix up size bits
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temp &= ~0x700000;
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temp |= size << 20;
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temp |= 1;
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temp &= ~0x1000;
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pci_write_config_dword(pcidev, i, temp);
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printk("Slot 0x%x: before banks wrote 0x%x\n", i, temp);
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// now see what the banks are.
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*cp = 0;
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*(cp + 0x1000) = 5;
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*(cp + 0x2000) = 6;
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*(cp + 0x4000) = 7;
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if (*cp) {
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printk("Slot 0x%x: two banks\n", i);
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// only two banks
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temp &= ~1;
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pci_write_config_dword(pcidev, i, temp);
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}
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else
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printk("Slot 0x%x: four banks\n", i);
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// compute real size
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size = (1<<size) * 0x400000;
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printk("Slot 0x%x: size is 0x%x\n", i, size);
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// advance cp for the next area to check
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cp += size;
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// is it two-sided
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temp |= 0x1800000;
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pci_write_config_dword(pcidev, i, temp);
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*cp = 0xaa;
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printk("Slot 0x%x: value at %p is 0x%x\n", i, cp, *cp);
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if (*cp != 0xaa) { // two side
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cp += size;
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temp &= ~0x1800000;
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pci_write_config_dword(pcidev, i, temp);
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printk("Slot %d: one-sided\n", i);
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}
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}
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cache_enable();
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return 0; //64*1024*1024;
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return 0; //64*1024*1024;
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}
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}
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