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UPSTREAM: Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"

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This reverts commit fec8872c9d.

The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.

After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.

BUG=none
BRANCH=none
TEST=none

Change-Id: I0a508bff03899c8b7bd7429bce653a7bea94bef0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 610d1c67b2
Original-Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Original-Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Original-Reviewed-on: https://review.coreboot.org/18369
Original-Tested-by: build bot (Jenkins)
Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Original-Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://chromium-review.googlesource.com/449827
This commit is contained in:
Daniel Kulesz 2017-02-15 14:35:43 +01:00 • committed by chrome-bot
parent 41e99b845a
commit 422e80b453
1 changed files with 0 additions and 3 deletions
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3
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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@ -72,9 +72,6 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
if (pDCTstat->Status & (1 << SB_Registered))
misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;