mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
bitworks support. 440bx fixes.
This commit is contained in:
Ronald G. Minnich
parent
7883f9ffc1
commit
3ec74f3298
12 changed files with 1114 additions and 147 deletions
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@ -488,6 +488,7 @@ struct superio {
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unsigned int keyboard, cir, game;
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unsigned int keyboard, cir, game;
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unsigned int gpio1, gpio2, gpio3;
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unsigned int gpio1, gpio2, gpio3;
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unsigned int acpi,hwmonitor;
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unsigned int acpi,hwmonitor;
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unsigned int mouse;
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};
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};
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struct southbridge;
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struct southbridge;
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44
src/mainboard/bitworks/ims/Config
Normal file
44
src/mainboard/bitworks/ims/Config
Normal file
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@ -0,0 +1,44 @@
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arch i386
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript cpu/i386/entry16.lds
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ldscript cpu/i386/entry32.lds
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mainboardinit cpu/i386/reset16.inc
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ldscript cpu/i386/reset16.lds
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mainboardinit superio/NSC/pc87351/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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northbridge intel/440bx
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southbridge intel/piix4e
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mainboardinit cpu/p6/earlymtrr.inc
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#mainboardinit ram/dump_northbridge.inc
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#mainboardinit ram/ramtest.inc
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#mainboardinit mainboard/bitworks/ims/do_ramtest.inc
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# These are for the dump SPD
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option SMBUS_MEM_DEVICE_START=(0xa << 3)
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option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START + 0x1)
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option SMBUS_MEM_DEVICE_INC=1
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#mainboardinit sdram/generic_dump_spd.inc
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nsuperio NSC/pc87351 keyboard=1 com1={1} com2={1} floppy=0 lpt=0 mouse=1
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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option PIIX4_DEVFN=0x38
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option CONFIG_UDELAY_TSC=1
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# These options control if the IDE controller is enabled in the
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# southbridge fixup code.
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option CONFIG_LINUXBIOS_ENABLE_IDE=1
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option CONFIG_LINUXBIOS_LEGACY_IDE=1
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object mainboard.o
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object irq_tables.o
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cpu p6
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cpu p5
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5
src/mainboard/bitworks/ims/do_ramtest.inc
Normal file
5
src/mainboard/bitworks/ims/do_ramtest.inc
Normal file
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@ -0,0 +1,5 @@
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mov $0x00000000, %eax
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mov $0x0004ffff, %ebx
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mov $16, %ecx
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CALLSP(ramtest)
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36
src/mainboard/bitworks/ims/irq_tables.c
Normal file
36
src/mainboard/bitworks/ims/irq_tables.c
Normal file
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@ -0,0 +1,36 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*1, /* there can be total devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0x38, /* Where the interrupt router lies (dev) */
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0xc00, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x7000, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x13, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* {0,0x60, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0},
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{0,0x58, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0},
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{0,0x50, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0},
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{0,0x48, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}}, 0x4, 0},
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{0,0x40, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x5, 0},
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{0,0x68, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x6, 0},
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{0,0x39, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0, 0},
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*/
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// USB bridge
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{0,0x3a, {{0x0, 0xdeb8}, {0x0, 0xdeb8}, {0x0, 0xdeb8}, {0x63, 0xdeb8}}, 0, 0},
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}
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};
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181
src/mainboard/bitworks/ims/mainboard.c
Normal file
181
src/mainboard/bitworks/ims/mainboard.c
Normal file
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@ -0,0 +1,181 @@
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#include <printk.h>
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#include <pci.h>
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#include <cpu/p5/io.h>
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void keyboard_on();
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void southbridge_fixup();
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// Body in the pixx4e/southbridge.c file
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void disable_seconday_ide(void);
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// this needs to be moved about a bit to northbridge.c etc.
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void mainboard_fixup()
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{
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struct pci_dev *pm_pcidev, *host_bridge_pcidev, *nic_pcidev;
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unsigned smbus_io, pm_io;
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unsigned int i, j;
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printk_debug("IMS mainboard_fixup()\n");
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#if 1
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pm_pcidev = pci_find_device(0x8086, 0x7113, 0);
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host_bridge_pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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#endif
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#if 1
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{
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u8 byte;
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u16 word;
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u32 dword;
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for(i = 0; i < 8; i++) {
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pci_read_config_byte(host_bridge_pcidev, 0x60 +i, &byte);
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printk_debug("DRB[i] = 0x%02x\n", byte);
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}
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pci_read_config_byte(host_bridge_pcidev, 0x57, &byte);
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printk_debug("DRAMC = 0x%02x\n", byte);
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pci_read_config_byte(host_bridge_pcidev, 0x74, &byte);
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printk_debug("RPS = 0x%02x\n", byte);
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pci_read_config_word(host_bridge_pcidev, 0x78, &word);
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printk_debug("PGPOL = 0x%04x\n", word);
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pci_read_config_dword(host_bridge_pcidev, 0x50, &dword);
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printk_debug("NBXCFG = 0x%04x\n", dword);
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}
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#endif
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#if 1
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printk_debug("Reset Control Register\n");
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outb(((inb(0xcf9) & 0x04) | 0x02), 0xcf9);
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printk_debug("port 92\n");
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outb((inb(0x92) & 0xFE), 0x92);
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printk_debug("Disable Nmi\n");
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outb(0, 0x70);
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printk_debug("enabling smbus\n");
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#if 0
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smbus_io = NewPciIo(0x10);
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#else
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smbus_io = 0xFFF0;
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#endif
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pci_write_config_dword(pm_pcidev, 0x90, smbus_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0xd2, (0x4 << 1) | 1); /* smbus enable */
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pci_write_config_word(pm_pcidev, 0x4, 1); /* iospace enable */
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printk_debug("enable pm functions\n");
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#if 0
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pm_io = NewPciIo(0x40);
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#else
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pm_io = 0xFF80;
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#endif
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pci_write_config_dword(pm_pcidev, 0x40, pm_io | 1); /* iobase addr */
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pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
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printk_debug("disabling smi\n");
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/* GLBEN */
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outw(0x00, pm_io + 0x20);
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/* GLBCTL */
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outl((1 << 24), pm_io + 0x28);
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printk_debug("Disable more pm stuff\n");
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/* PMEN */
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outw((1 << 8), pm_io + 0x02);
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/* PMCNTRL */
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outw((0x5 << 10) , pm_io + 0x4);
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/* PMTMR */
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outl(0, pm_io + 0x08);
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/* GPEN */
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outw(0, pm_io + 0x0e);
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/* PCNTRL */
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outl(0, pm_io + 0x10);
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/* GLBSTS */
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/* DEVSTS */
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/* GLBEN see above */
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/* GLBCTL see above */
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/* DEVCTL */
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outl(0, pm_io + 0x2c);
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/* GPIREG */
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/* GPOREG */
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printk_debug("Set the subsystem vendor id\n");
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pci_write_config_word(host_bridge_pcidev, 0x2c, 0x8086);
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printk_debug("Disabling pm stuff in pci config space\n");
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#define MAX_COUNTERS
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#ifndef MAX_COUNTERS
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/* counters to 0 */
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#define WHICH_COUNTERS(min,max) min
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#else
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/* max out the counters */
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#define WHICH_COUNTERS(min,max) max
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#endif
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/* CNTA */
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pci_write_config_dword(pm_pcidev, 0x44, WHICH_COUNTERS(0x004000f0, 0xFFFFFFFF));
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/* CNTB */
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pci_write_config_dword(pm_pcidev, 0x48, WHICH_COUNTERS(0x00000400, 0x007c07df));
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/* GPICTL */
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pci_write_config_dword(pm_pcidev, 0x4c, 0);
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/* DEVRESD */
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pci_write_config_dword(pm_pcidev, 0x50, 0);
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/* DEVACTA */
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pci_write_config_dword(pm_pcidev, 0x54, 0);
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/* DEVACTB */
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pci_write_config_dword(pm_pcidev, 0x58, 0);
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/* DEVRESA */
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pci_write_config_dword(pm_pcidev, 0x5c, 0);
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/* DEVRESB */
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pci_write_config_dword(pm_pcidev, 0x60, 0);
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/* DEVRESC */
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pci_write_config_dword(pm_pcidev, 0x64, 0); /* might kill the serial port */
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/* DEVRESE */
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pci_write_config_dword(pm_pcidev, 0x68, 0);
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/* DEVRESF */
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pci_write_config_dword(pm_pcidev, 0x6c, 0);
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/* DEVRESG */
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pci_write_config_dword(pm_pcidev, 0x70, 0);
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/* DEVRESH */
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pci_write_config_dword(pm_pcidev, 0x74, 0);
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/* DEVRESI */
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pci_write_config_dword(pm_pcidev, 0x78, 0);
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/* DEVRESJ */
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pci_write_config_dword(pm_pcidev, 0x7c, 0);
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#endif
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#if 1
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/* Verify that smi is disabled */
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printk_debug("Testing SMI\r\n");
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{
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u32 value;
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pci_read_config_dword(pm_pcidev, 0x58, &value);
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pci_write_config_dword(pm_pcidev, 0x58, value | (1 << 25));
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}
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outb(inb(0xb2), 0xb2);
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printk_debug("SMI disabled\r\n");
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#endif
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disable_secondary_ide();
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printk_debug( "Calling southbridge_fixup()\r\n");
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southbridge_fixup();
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}
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@ -2,6 +2,17 @@ jmp intel_440_out
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#define USE_SPD 1
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#define USE_SPD 1
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#define REGISTERED_DRAM $0x10
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#define NONREGISTERED_DRAM $0x08
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#define REGISTERED_DRAM_REGISTER $0x57
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#define SMBUS_MEM_DEVICE_0 (0xa << 3)
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#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
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#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
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#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
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#define LAST_SMBUS_MEM_DEVICE (SMBUS_MEM_DEVICE_3)
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#define CS_WRITE_BYTE(addr, byte) \
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#define CS_WRITE_BYTE(addr, byte) \
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movl $addr, %eax ; \
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movl $addr, %eax ; \
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movl $byte, %edx ; \
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movl $byte, %edx ; \
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@ -106,8 +117,9 @@ jmp intel_440_out
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#define SET_NBXCFG \
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#define SET_NBXCFG \
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CS_WRITE_LONG(0x50, 0xff00a00c)
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CS_WRITE_LONG(0x50, 0xff00a00c)
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/* This insures refresh is off */
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#define SET_DRAMC \
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#define SET_DRAMC \
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CS_WRITE_BYTE(0x57, 0x8) \
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CS_WRITE_BYTE(0x57, 0x8)
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/* PAM - Programmable Attribute Map Registers */
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/* PAM - Programmable Attribute Map Registers */
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/* Ideally we want to enable all of these as DRAM and teach
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/* Ideally we want to enable all of these as DRAM and teach
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@ -196,12 +208,6 @@ setup_smbus:
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outb %al, %dx
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outb %al, %dx
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RET_LABEL(setup_smbus)
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RET_LABEL(setup_smbus)
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#define SMBUS_MEM_DEVICE_0 (0xa << 3)
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#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
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#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
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#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
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smbus_wait_until_ready:
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smbus_wait_until_ready:
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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1: inb %dx, %al
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1: inb %dx, %al
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@ -262,106 +268,275 @@ smbus_read_byte:
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1:
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1:
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RETSP
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RETSP
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configure_rps_pgpol_drb:
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/*
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* Routine: spd_set_drb
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* Arguments: None
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*
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* Trashed: %eax, %ebx, %ecx, %edx, %esi, %edi, %ebp, %esp, %eflags
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* Effects: Uses serial presence detect to set the
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* DRB registers which holds the ending memory address assigned
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|
* to each DIMM.
|
||||||
|
* Notes: %ebp holds the currently detected end of memory.
|
||||||
|
* %ebx holds the configuration port & SMBUS_MEM_DEVICE for
|
||||||
|
* the current iteration through the loop.
|
||||||
|
* %edi holds the memory size for the first side of the DIMM.
|
||||||
|
* %esi holds the memory size for the second side of the DIMM.
|
||||||
|
* memory size is represent as a power of 2.
|
||||||
|
* An unset memory size is represented as -1 ie. 0xFFFFFFFF
|
||||||
|
*/
|
||||||
|
|
||||||
/* %bl is the row index */
|
spd_set_drb:
|
||||||
xorl %ebx, %ebx
|
xorl %ebp, %ebp /* clear the memory address */
|
||||||
|
movl $((0x60 << 16) |SMBUS_MEM_DEVICE_0), %ebx
|
||||||
/* %si is the aggregation of bits for RPS */
|
spd_set_drb_loop_top:
|
||||||
xorl %esi, %esi
|
|
||||||
|
|
||||||
/* %di has bits to be set in PGPOL */
|
|
||||||
xorl %edi, %edi
|
xorl %edi, %edi
|
||||||
|
subl $1, %edi
|
||||||
|
xorl %esi, %esi
|
||||||
|
subl $1, %esi
|
||||||
|
|
||||||
/* %cx holds the cumulative memory size of DIMMs */
|
movb $3, %bh /* rows */
|
||||||
xorl %ecx, %ecx
|
CALLSP(smbus_read_byte)
|
||||||
|
jnz 20f
|
||||||
|
andl $0xf, %eax
|
||||||
|
addl %eax, %edi
|
||||||
|
|
||||||
|
movb $4, %bh /* columns */
|
||||||
|
CALLSP(smbus_read_byte)
|
||||||
|
andl $0xf, %eax
|
||||||
|
addl %eax, %edi
|
||||||
|
|
||||||
next_row:
|
movb $17, %bh /* banks */
|
||||||
movzx %bl, %dx
|
CALLSP(smbus_read_byte)
|
||||||
shl $16, %ebx
|
andl $0xff, %eax
|
||||||
shr $1, %dx
|
bsrl %eax, %ecx
|
||||||
mov $((5 << 8) | SMBUS_MEM_DEVICE_0), %bx
|
addl %ecx, %edi
|
||||||
or %dx, %bx
|
|
||||||
CALLSP(smbus_read_byte)
|
|
||||||
jnz shift_before_moving_on
|
|
||||||
shr $16, %ebx
|
|
||||||
|
|
||||||
testb $2, %al
|
/* Get the module data width and convert it to a power of two */
|
||||||
jnz two_rows
|
movb $7, %bh /* (high byte) */
|
||||||
testb $1, %bl
|
CALLSP(smbus_read_byte)
|
||||||
/* this used to be jnz but seems it should be jz */
|
andl $0xff, %eax
|
||||||
jz ready_for_next_row
|
movl %eax, %ecx
|
||||||
|
shll $8, %ecx
|
||||||
|
|
||||||
two_rows:
|
movb $6, %bh /* (low byte) */
|
||||||
movzx %bl, %dx
|
CALLSP(smbus_read_byte)
|
||||||
shl $16, %ebx
|
andl $0xff, %eax
|
||||||
shr $1, %dx
|
orl %eax, %ecx
|
||||||
mov $((4 << 8) | SMBUS_MEM_DEVICE_0), %bx
|
bsrl %ecx, %eax
|
||||||
or %dx, %bx
|
addl %eax, %edi
|
||||||
CALLSP(smbus_read_byte)
|
|
||||||
shr $16, %ebx
|
|
||||||
|
|
||||||
subb $8, %al
|
/* now I have the ram size in bits as a power of two (less 1) */
|
||||||
shrd $2, %ax, %si
|
subl $25, %edi /* Make it multiples of 8MB */
|
||||||
|
|
||||||
movzx %bl, %dx
|
/* side two */
|
||||||
shl $16, %ebx
|
movb $5, %bh /* number of physical banks */
|
||||||
shr $1, %dx
|
CALLSP(smbus_read_byte)
|
||||||
mov $((17 << 8) | SMBUS_MEM_DEVICE_0), %bx
|
cmp $1, %al
|
||||||
or %dx, %bx
|
jbe 20f
|
||||||
CALLSP(smbus_read_byte)
|
|
||||||
shr $16, %ebx
|
|
||||||
|
|
||||||
cmpb $4, %al
|
/* for now only handle the symmetrical case */
|
||||||
sete %al
|
movl %edi, %esi
|
||||||
shrd $1, %ax, %di
|
20:
|
||||||
|
/* Compute the end address for the DRB register */
|
||||||
movzx %bl, %dx
|
cmpl $8, %edi /* Ignore the dimm if it is over 2GB */
|
||||||
shl $16, %ebx
|
jae 21f
|
||||||
shr $1, %dx
|
movl $1, %eax
|
||||||
mov $((31 << 8) | SMBUS_MEM_DEVICE_0), %bx
|
movl %edi, %ecx
|
||||||
or %dx, %bx
|
shll %cl, %eax
|
||||||
CALLSP(smbus_read_byte)
|
addl %eax, %ebp
|
||||||
shr $16, %ebx
|
21:
|
||||||
|
/* Write the computed value for the first half of the DIMM */
|
||||||
shr $1, %al
|
movl %ebp, %edx /* value to write into %edx */
|
||||||
xorb %ah, %ah
|
movl %ebx, %eax
|
||||||
add %ax, %cx
|
shrl $16, %eax /* port address into %eax */
|
||||||
movzx %cx, %edx
|
|
||||||
movzx %bl, %eax
|
|
||||||
addl $0x60, %eax
|
|
||||||
PCI_WRITE_CONFIG_BYTE
|
PCI_WRITE_CONFIG_BYTE
|
||||||
|
|
||||||
|
/* Compute the end address for the DRB register */
|
||||||
|
cmpl $8, %esi /* Ignore the dimm if it is over 2GB */
|
||||||
|
jae 30f
|
||||||
|
mov $1, %eax
|
||||||
|
movl %esi, %ecx
|
||||||
|
shll %cl, %eax
|
||||||
|
addl %eax, %ebp
|
||||||
|
30:
|
||||||
|
/* Write the comuputed value for the second half of the DIMM */
|
||||||
|
movl %ebp, %edx /* value to write into %edx */
|
||||||
|
movl %ebx, %eax
|
||||||
|
shrl $16, %eax /* port address into %eax */
|
||||||
|
addl $1, %eax /* The second half uses one port high */
|
||||||
|
PCI_WRITE_CONFIG_BYTE
|
||||||
|
|
||||||
|
addl $0x00020001, %ebx /* increment the smbus device & the config port */
|
||||||
|
cmpb $SMBUS_MEM_DEVICE_3, %bl /* see if I have reached the end */
|
||||||
|
jbe spd_set_drb_loop_top
|
||||||
|
|
||||||
|
/* o.k. I'm done return now */
|
||||||
|
RET_LABEL(spd_set_drb)
|
||||||
|
|
||||||
|
|
||||||
|
spd_set_dramc:
|
||||||
|
|
||||||
|
/* auto detect if ram is registered or not. */
|
||||||
|
/* The DRAMC register also contorls the refresh rate but we can't
|
||||||
|
* set that here because we must leave refresh disabled.
|
||||||
|
* see: spd_enable_refresh
|
||||||
|
*/
|
||||||
|
/* Find the first dimm and assume the rest are the same */
|
||||||
|
/* Load the smbus device and port int %ebx */
|
||||||
|
mov $((21 << 8) | SMBUS_MEM_DEVICE_0), %bx
|
||||||
|
1: CALLSP(smbus_read_byte)
|
||||||
|
jnz 2f
|
||||||
|
andl $0x12, %eax
|
||||||
|
jmp spd_set_dramc_out
|
||||||
|
|
||||||
|
2: addl $1, %ebx /* increment the device */
|
||||||
|
cmpb $LAST_SMBUS_MEM_DEVICE, %bl
|
||||||
|
jbe 1b
|
||||||
|
/* We couldn't find anything we must have no memory */
|
||||||
|
jmp no_memory
|
||||||
|
|
||||||
|
spd_set_dramc_out:
|
||||||
|
testb $0x12, %al
|
||||||
|
jz 2f
|
||||||
|
movl REGISTERED_DRAM, %eax
|
||||||
jmp 1f
|
jmp 1f
|
||||||
|
2: movl NONREGISTERED_DRAM, %eax
|
||||||
shift_before_moving_on:
|
1: movl %eax, %edx
|
||||||
shr $16, %ebx
|
movl REGISTERED_DRAM_REGISTER, %eax
|
||||||
ready_for_next_row:
|
|
||||||
shr $2, %si
|
|
||||||
shr $1, %di
|
|
||||||
movzx %cx, %edx
|
|
||||||
movzx %bl, %eax
|
|
||||||
addl $0x60, %eax
|
|
||||||
PCI_WRITE_CONFIG_BYTE
|
PCI_WRITE_CONFIG_BYTE
|
||||||
|
|
||||||
|
RET_LABEL(spd_set_dramc)
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Routine: spd_set_rps
|
||||||
|
* Arguments: None
|
||||||
|
*
|
||||||
|
* Trashed: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
|
||||||
|
* Effects: Uses serial presence detect to set the row size
|
||||||
|
* on a given DIMM
|
||||||
|
* Notes: %esi accumulates the row sizes of all of the DIMMs
|
||||||
|
* %ecx holds the current bit into into %esi
|
||||||
|
* %bl holds the current SMBUS device
|
||||||
|
* FIXME: Check for illegal/unsupported ram configurations and abort
|
||||||
|
|
||||||
|
Richard Smith ported this from the 440gx board.
|
||||||
|
one thing to note is that the polarity of an error from
|
||||||
|
smbus_read_byte is opposite of the 440gx
|
||||||
|
*/
|
||||||
|
|
||||||
|
spd_set_rps:
|
||||||
|
/* The RPS register holds the size of a ``page'' of DRAM on each DIMM */
|
||||||
|
/* default all page sizes to 2KB */
|
||||||
|
xorl %esi, %esi
|
||||||
|
/* Index into %esi of bit to set */
|
||||||
|
movl $0 , %ecx
|
||||||
|
/* Load the smbus device into %ebx */
|
||||||
|
movl $SMBUS_MEM_DEVICE_0, %ebx
|
||||||
|
|
||||||
|
1: movb $4, %bh
|
||||||
|
CALLSP(smbus_read_byte) /* row address bits */
|
||||||
|
jnz 2f
|
||||||
|
andl $0xf, %eax
|
||||||
|
movl %eax, %edi
|
||||||
|
|
||||||
|
/* Number of colums indicates which row page size to use */
|
||||||
|
subl $8, %edi
|
||||||
|
jbe 2f
|
||||||
|
/* FIXME: do something with page sizes greather than 8KB!! */
|
||||||
|
shll %cl, %edi
|
||||||
|
orl %edi, %esi
|
||||||
|
/* side two */
|
||||||
|
movb $5, %bh
|
||||||
|
CALLSP(smbus_read_byte) /* number of physical banks */
|
||||||
|
cmp $1, %al
|
||||||
|
jbe 2f
|
||||||
|
/* for now only handle the symmtrical case */
|
||||||
|
shll $2, %edi
|
||||||
|
/* one too many shifts here. */
|
||||||
|
/* shll %cl, %edi*/
|
||||||
|
orl %edi, %esi
|
||||||
|
|
||||||
|
2: addl $1, %ebx /* increment the device */
|
||||||
|
addl $4, %ecx /* increment the shift count */
|
||||||
|
cmpb $SMBUS_MEM_DEVICE_3, %bl
|
||||||
|
jbe 1b
|
||||||
|
|
||||||
|
/* next block is for Ron's attempt to get registered to work. */
|
||||||
|
/* we have just verified that we have to have this code. It appears that
|
||||||
|
* the registered SDRAMs do indeed set the RPS wrong. sheesh.
|
||||||
|
*/
|
||||||
|
/* at this point, %esi holds the RPS for all ram.
|
||||||
|
* we have verified that for registered DRAM the values are
|
||||||
|
* 1/2 the size they should be. So we test for registered
|
||||||
|
* and then double the sizes if needed.
|
||||||
|
*/
|
||||||
|
movl $0x57, %eax
|
||||||
|
PCI_READ_CONFIG_BYTE
|
||||||
|
|
||||||
|
/* is it registered? */
|
||||||
|
testb $0x10, %eax
|
||||||
|
jz 1f
|
||||||
|
|
||||||
|
/* BIOS makes weird page size for registered! */
|
||||||
|
/* what we have found is you need to set the EVEN banks to
|
||||||
|
* twice the size. Fortunately there is a very easy way to
|
||||||
|
* do this. First, read the WORD value of register 0x74.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* now to double the size of the EVEN banks we only need to add 1 */
|
||||||
|
/* because the size is log2
|
||||||
|
*/
|
||||||
|
addl $0x1111, %esi
|
||||||
|
/* now write that final value of %esi into register 0x74 */
|
||||||
1:
|
1:
|
||||||
inc %bl
|
movl %esi, %ecx
|
||||||
cmp MAX_ROWS, %bl
|
|
||||||
jb next_row
|
|
||||||
|
|
||||||
/* Now to finally write the RPS and PGPOL registers */
|
|
||||||
|
|
||||||
movzx %si, %ecx
|
|
||||||
movl $0x74, %eax
|
movl $0x74, %eax
|
||||||
PCI_WRITE_CONFIG_WORD
|
PCI_WRITE_CONFIG_WORD
|
||||||
|
|
||||||
mov %di, %cx
|
RET_LABEL(spd_set_rps)
|
||||||
movzx %ch, %edx
|
|
||||||
movl $0x79, %eax
|
|
||||||
PCI_WRITE_CONFIG_BYTE
|
|
||||||
|
|
||||||
RET_LABEL(configure_rps_pgpol_drb)
|
spd_set_pgpol:
|
||||||
|
/* The PGPOL register stores the number of logical banks per DIMM,
|
||||||
|
* and number of clocks the DRAM controller waits in the idle
|
||||||
|
* state.
|
||||||
|
*/
|
||||||
|
/* default all bank counts 2 */
|
||||||
|
xorl %esi, %esi
|
||||||
|
/* Index into %esi of bit to set */
|
||||||
|
movl $0 , %ecx
|
||||||
|
/* Load the smbus device into %ebx */
|
||||||
|
movl $SMBUS_MEM_DEVICE_0, %ebx
|
||||||
|
|
||||||
|
1: movb $17, %bh
|
||||||
|
CALLSP(smbus_read_byte) /* logical banks */
|
||||||
|
jnz 2f
|
||||||
|
cmp $0x4, %eax
|
||||||
|
jl 2f
|
||||||
|
movl $0x1, %eax
|
||||||
|
shll %cl, %eax
|
||||||
|
orl %eax, %esi
|
||||||
|
/* side two */
|
||||||
|
movb $5, %bh
|
||||||
|
CALLSP(smbus_read_byte) /* number of physical banks */
|
||||||
|
cmp $1, %al
|
||||||
|
jbe 2f
|
||||||
|
/* for now only handle the symmtrical case */
|
||||||
|
movl $0x2, %eax
|
||||||
|
shll %cl, %eax
|
||||||
|
orl %eax, %esi
|
||||||
|
|
||||||
|
2: addl $1, %ebx /* increment the device */
|
||||||
|
addl $2, %ecx /* increment the shift count */
|
||||||
|
cmpb $SMBUS_MEM_DEVICE_3, %bl
|
||||||
|
jbe 1b
|
||||||
|
|
||||||
|
shll $8, %esi
|
||||||
|
orl $0x7, %esi /* 32 clocks idle time */
|
||||||
|
movl %esi, %ecx
|
||||||
|
movl $0x78, %eax
|
||||||
|
PCI_WRITE_CONFIG_WORD
|
||||||
|
RET_LABEL(spd_set_pgpol)
|
||||||
|
|
||||||
configure_sdramc:
|
configure_sdramc:
|
||||||
movl $((18 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
movl $((18 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
||||||
|
|
@ -381,28 +556,6 @@ configure_sdramc:
|
||||||
2:
|
2:
|
||||||
RET_LABEL(configure_sdramc)
|
RET_LABEL(configure_sdramc)
|
||||||
|
|
||||||
spd_set_dramc:
|
|
||||||
movl $((21 << 8) | SMBUS_MEM_DEVICE_0), %ebx
|
|
||||||
1: CALLSP(smbus_read_byte)
|
|
||||||
jnz 2f
|
|
||||||
andl $0x12, %eax
|
|
||||||
jmp spd_set_dramc_out
|
|
||||||
|
|
||||||
2: addl $1, %ebx /* increment the device */
|
|
||||||
cmpb $SMBUS_MEM_DEVICE_3, %bl
|
|
||||||
jbe 1b
|
|
||||||
jmp no_memory
|
|
||||||
|
|
||||||
spd_set_dramc_out:
|
|
||||||
testb $0x2, %al
|
|
||||||
movl $8, %eax
|
|
||||||
jz 1f
|
|
||||||
movl $0x10, %eax
|
|
||||||
1: movl %eax, %edx
|
|
||||||
movl $0x57, %eax
|
|
||||||
PCI_WRITE_CONFIG_BYTE
|
|
||||||
RET_LABEL(spd_set_dramc)
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Routine: spd_enable_refresh
|
* Routine: spd_enable_refresh
|
||||||
|
|
@ -498,9 +651,11 @@ spd_set_nbxcfg:
|
||||||
ram_set_spd_registers:
|
ram_set_spd_registers:
|
||||||
CALL_LABEL(enable_smbus)
|
CALL_LABEL(enable_smbus)
|
||||||
CALL_LABEL(setup_smbus)
|
CALL_LABEL(setup_smbus)
|
||||||
CALL_LABEL(configure_sdramc)
|
CALL_LABEL(spd_set_drb)
|
||||||
CALL_LABEL(configure_rps_pgpol_drb)
|
|
||||||
CALL_LABEL(spd_set_dramc)
|
CALL_LABEL(spd_set_dramc)
|
||||||
|
CALL_LABEL(spd_set_rps)
|
||||||
|
CALL_LABEL(configure_sdramc)
|
||||||
|
CALL_LABEL(spd_set_pgpol)
|
||||||
CALL_LABEL(spd_set_nbxcfg)
|
CALL_LABEL(spd_set_nbxcfg)
|
||||||
|
|
||||||
RET_LABEL(ram_set_spd_registers)
|
RET_LABEL(ram_set_spd_registers)
|
||||||
|
|
|
||||||
|
|
@ -1,2 +1,5 @@
|
||||||
|
option CONFIG_ENABLE_MOUSE_IRQ12=1
|
||||||
|
option CONFIG_ENABLE_KBCCS=0
|
||||||
|
option CONFIG_SETUP_RTC=1
|
||||||
object southbridge.o
|
object southbridge.o
|
||||||
object smbus.o USE_PIIX4E_SMBUS
|
object smbus.o USE_PIIX4E_SMBUS
|
||||||
|
|
|
||||||
|
|
@ -68,11 +68,39 @@ southbridge_fixup()
|
||||||
pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
|
pci_write_config_byte(pm_pcidev, 0x80, 1); /* enable pm io address */
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if CONFIG_SETUP_RTC==1
|
||||||
|
printk_info( "Setting up RTC\n");
|
||||||
|
rtc_init(0);
|
||||||
|
#endif
|
||||||
|
|
||||||
printk_info("done.\n");
|
printk_info("done.\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// Disables the secondary ide interface.
|
||||||
|
// This tri-states the signals on the seconday ide
|
||||||
|
// interface. Should free up the irq as well.
|
||||||
|
void disable_secondary_ide(void)
|
||||||
|
{
|
||||||
|
struct pci_dev *pcidev;
|
||||||
|
volatile unsigned char regval;
|
||||||
|
|
||||||
|
printk_info( "Disableing secondary ide controller\n");
|
||||||
|
|
||||||
|
pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL);
|
||||||
|
|
||||||
|
pci_read_config_byte(pcidev, 0xb1, ®val);
|
||||||
|
regval &= 0xef;
|
||||||
|
pci_write_config_byte(pcidev, 0xb1, regval);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
This functions is now very misnamed as it deals with much more
|
||||||
|
than just the nvram
|
||||||
|
*/
|
||||||
void nvram_on()
|
void nvram_on()
|
||||||
{
|
{
|
||||||
|
|
||||||
/*; now set up PIIX4e registers 4e and 4f for nvram access.
|
/*; now set up PIIX4e registers 4e and 4f for nvram access.
|
||||||
; 4e will have value 0xc3, 4f will have value 2
|
; 4e will have value 0xc3, 4f will have value 2
|
||||||
; we are going to PIIX4 function 0; the PIIX4 is device 0x12.
|
; we are going to PIIX4 function 0; the PIIX4 is device 0x12.
|
||||||
|
|
@ -84,11 +112,39 @@ void nvram_on()
|
||||||
*/
|
*/
|
||||||
|
|
||||||
struct pci_dev *pcidev;
|
struct pci_dev *pcidev;
|
||||||
|
volatile unsigned char regval;
|
||||||
|
|
||||||
printk_info( "Enabling extended BIOS access...");
|
printk_info( "Enabling extended BIOS access\n");
|
||||||
|
|
||||||
pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL);
|
pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL);
|
||||||
if (pcidev) pci_write_config_word(pcidev, 0x4e, 0x03c3);
|
|
||||||
|
// Need to enable the full ISA bus rather than EIO which
|
||||||
|
// is enabled default
|
||||||
|
|
||||||
|
printk_info( "Enabling Full ISA Mode\n");
|
||||||
|
pci_read_config_byte(pcidev, 0xb0, ®val);
|
||||||
|
regval |= 0x01;
|
||||||
|
pci_write_config_byte(pcidev, 0xb0, regval);
|
||||||
|
|
||||||
|
// RAS 6/24/03
|
||||||
|
// Datasheet says if you enable the APIC then IRQ8 must
|
||||||
|
// not be setup as a GPI. Default is GPI so set this
|
||||||
|
// before eaabling the APIC
|
||||||
|
|
||||||
|
printk_info( "Enabling IRQ8\n");
|
||||||
|
|
||||||
|
pci_read_config_byte(pcidev, 0xb1, ®val);
|
||||||
|
regval |= 0x40;
|
||||||
|
pci_write_config_byte(pcidev, 0xb1, regval);
|
||||||
|
|
||||||
|
|
||||||
|
#if CONFIG_ENABLE_MOUSE_IRQ12==0
|
||||||
|
printk_info( "Disableing Mouse IRQ12 on piix4e\n");
|
||||||
|
if (pcidev) pci_write_config_word(pcidev, 0x4e, 0x03e1);
|
||||||
|
#else
|
||||||
|
printk_info( "Enabling Mouse IRQ12 on piix4e\n");
|
||||||
|
if (pcidev) pci_write_config_word(pcidev, 0x4e, 0x03f1);
|
||||||
|
#endif
|
||||||
|
|
||||||
printk_info("done.\n");
|
printk_info("done.\n");
|
||||||
post_code(0x91);
|
post_code(0x91);
|
||||||
|
|
@ -98,12 +154,14 @@ void nvram_on()
|
||||||
// for now, I am putting in the old keyboard code, until we figure out
|
// for now, I am putting in the old keyboard code, until we figure out
|
||||||
// the best way to do this -- RGM
|
// the best way to do this -- RGM
|
||||||
|
|
||||||
#ifdef NO_KEYBOARD
|
#if (NO_KEYBOARD==1)
|
||||||
void keyboard_on()
|
void keyboard_on()
|
||||||
{
|
{
|
||||||
|
printk_debug( __FUNCTION__ ": Skipping Keyboard\n");
|
||||||
post_code(0x94);
|
post_code(0x94);
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
|
||||||
void keyboard_on()
|
void keyboard_on()
|
||||||
{
|
{
|
||||||
u32 controlbits;
|
u32 controlbits;
|
||||||
|
|
@ -115,15 +173,21 @@ void keyboard_on()
|
||||||
pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL);
|
pcidev = pci_find_device(0x8086, 0x7110, (void *)NULL);
|
||||||
|
|
||||||
if (! pcidev) {
|
if (! pcidev) {
|
||||||
printk_err( __FUNCTION__ "Can't find dev 0x7110\n");
|
printk_err( __FUNCTION__ ": Can't find dev 0x7110\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
/* oh no, we are setting this below. Fix it later. */
|
|
||||||
/* to do -- changed these to PciReadByte */
|
// RAS 6/24/03
|
||||||
|
// If your super IO dosen't have IO decodeing of ports 60 and 64
|
||||||
|
// builtin then you need to enable this. Default is off since most
|
||||||
|
// superio don't need the extra help.
|
||||||
|
|
||||||
|
#if CONFIG_ENABLE_KBCCS == 1
|
||||||
pci_read_config_byte(pcidev, 0x4e, ®val);
|
pci_read_config_byte(pcidev, 0x4e, ®val);
|
||||||
printk_debug( __FUNCTION__ "regcal at 0x4e is 0x%x\n", regval);
|
printk_debug( __FUNCTION__ ": regcal at 0x4e is 0x%x\n", regval);
|
||||||
regval |= 0x2;
|
regval |= 0x2;
|
||||||
pci_write_config_byte(pcidev, 0x4e, regval);
|
pci_write_config_byte(pcidev, 0x4e, regval);
|
||||||
|
#endif
|
||||||
|
|
||||||
/* this is a hole in the linux pci function design. You get devfn 0,
|
/* this is a hole in the linux pci function design. You get devfn 0,
|
||||||
* but you can't select functions 1-3 using the pci_find_device!
|
* but you can't select functions 1-3 using the pci_find_device!
|
||||||
|
|
@ -143,7 +207,15 @@ void keyboard_on()
|
||||||
pcibios_write_config_dword(0, devfn, 0x60, controlbits);
|
pcibios_write_config_dword(0, devfn, 0x60, controlbits);
|
||||||
|
|
||||||
/* now keyboard should work, ha ha. */
|
/* now keyboard should work, ha ha. */
|
||||||
pc_keyboard_init();
|
|
||||||
|
// RAS 6/24/03
|
||||||
|
// Me thinks that calling the keyboard init stuff here is incorrect
|
||||||
|
// since you may not have the keyboard _realley_ enabled yet if its in
|
||||||
|
// a superio. I've left it up to the superio code to call it
|
||||||
|
// but perhaps it should be a mainboard config item?
|
||||||
|
|
||||||
|
// pc_keyboard_init();
|
||||||
|
|
||||||
post_code(0x94);
|
post_code(0x94);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
1
src/superio/NSC/pc87351/Config
Normal file
1
src/superio/NSC/pc87351/Config
Normal file
|
|
@ -0,0 +1 @@
|
||||||
|
option ENABLE_MOUSE=0
|
||||||
50
src/superio/NSC/pc87351/setup_serial.inc
Normal file
50
src/superio/NSC/pc87351/setup_serial.inc
Normal file
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* Enable the serial peripheral devices on the NSC Super IO chip PC87351
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* The base address is 0x15c, 0x2e, depending on config bytes */
|
||||||
|
|
||||||
|
#define SIO_BASE $0x2e
|
||||||
|
#define SIO_INDEX SIO_BASE
|
||||||
|
#define SIO_DATA SIO_BASE+1
|
||||||
|
|
||||||
|
#define SIO_READ(ldn, index) \
|
||||||
|
mov SIO_BASE, %dx ; \
|
||||||
|
mov $0x07, %al ; \
|
||||||
|
outb %al, %dx ; \
|
||||||
|
inc %dx ; \
|
||||||
|
mov ldn, %al ; \
|
||||||
|
outb %al, %dx ; \
|
||||||
|
dec %dx ; \
|
||||||
|
mov index, %al ; \
|
||||||
|
outb %al, %dx ; \
|
||||||
|
inc %dx ; \
|
||||||
|
inb %dx, %al ;
|
||||||
|
|
||||||
|
#define SIO_WRITE(ldn, index, data) \
|
||||||
|
mov SIO_BASE, %dx ; \
|
||||||
|
mov $0x07, %al ; \
|
||||||
|
outb %al, %dx ; \
|
||||||
|
inc %dx ; \
|
||||||
|
mov ldn, %al ; \
|
||||||
|
outb %al, %dx ; \
|
||||||
|
dec %dx ; \
|
||||||
|
mov index, %al ; \
|
||||||
|
outb %al, %dx ; \
|
||||||
|
inc %dx ; \
|
||||||
|
mov data, %al ; \
|
||||||
|
outb %al, %dx ;
|
||||||
|
|
||||||
|
|
||||||
|
/* At boot up the chip is in configure mode so don't worry
|
||||||
|
* about getting it there just configure some peripherals.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* enable serial 1 Logical device 3 */
|
||||||
|
// the default address is 0x3f8
|
||||||
|
SIO_WRITE($0x03, $0x30, $0x01)
|
||||||
|
|
||||||
|
// enable serial 2 Logical device 2
|
||||||
|
// the default address is 0x2f8
|
||||||
|
SIO_WRITE($0x02, $0x30, $0x01)
|
||||||
365
src/superio/NSC/pc87351/superio.c
Normal file
365
src/superio/NSC/pc87351/superio.c
Normal file
|
|
@ -0,0 +1,365 @@
|
||||||
|
/*
|
||||||
|
This is the superio config file for the National Semiconductor
|
||||||
|
pc87351 superio chip
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <pci.h>
|
||||||
|
#include <cpu/p5/io.h>
|
||||||
|
#include <serial_subr.h>
|
||||||
|
#include <printk.h>
|
||||||
|
|
||||||
|
// just define these here. We may never need them anywhere else
|
||||||
|
#define FLOPPY_DEVICE 0
|
||||||
|
#define PARALLEL_DEVICE 1
|
||||||
|
#define COM1_DEVICE 3
|
||||||
|
#define COM2_DEVICE 2
|
||||||
|
#define SYSTEM_WAKEUP_CONTROL 4
|
||||||
|
#define KBC_DEVICE 6
|
||||||
|
#define MOUSE_DEVICE 5
|
||||||
|
#define GPIO_DEVICE 7
|
||||||
|
#define FAN_SPEED_DEVICE 8
|
||||||
|
|
||||||
|
#define FLOPPY_DEFAULT_IOBASE 0x3f0
|
||||||
|
#define FLOPPY_DEFAULT_IRQ 6
|
||||||
|
#define FLOPPY_DEFAULT_DRQ 2
|
||||||
|
#define PARALLEL_DEFAULT_IOBASE 0x378
|
||||||
|
#define PARALLEL_DEFAULT_IRQ 7
|
||||||
|
#define PARALLEL_DEFAULT_DRQ 4 /* No dma */
|
||||||
|
#define COM1_DEFAULT_IOBASE 0x3f8
|
||||||
|
#define COM1_DEFAULT_IRQ 4
|
||||||
|
#define COM1_DEFAULT_BAUD 115200
|
||||||
|
#define COM2_DEFAULT_IOBASE 0x2f8
|
||||||
|
#define COM2_DEFAULT_IRQ 3
|
||||||
|
#define COM2_DEFAULT_BAUD 115200
|
||||||
|
#define KBC_DEFAULT_IOBASE0 0x60
|
||||||
|
#define KBC_DEFAULT_IOBASE1 0x64
|
||||||
|
#define KBC_DEFAULT_IRQ0 0x1
|
||||||
|
#define MOUSE_DEFAULT_IRQ0 0x0c
|
||||||
|
|
||||||
|
// funny how all these chips are "pnp compatible", and they're all different.
|
||||||
|
#define PNP_BASE_ADDR 0x2e
|
||||||
|
|
||||||
|
static void setup_devices(struct superio *sio);
|
||||||
|
|
||||||
|
struct superio_control superio_NSC_pc87351_control = {
|
||||||
|
pre_pci_init: (void *) 0,
|
||||||
|
init: setup_devices,
|
||||||
|
finishup: (void *) 0,
|
||||||
|
defaultport: PNP_BASE_ADDR,
|
||||||
|
name: "National Semiconductor pc87351"
|
||||||
|
};
|
||||||
|
|
||||||
|
void
|
||||||
|
enter_pnp(struct superio *sio)
|
||||||
|
{
|
||||||
|
// The 87351 dosen't seem to need this
|
||||||
|
// unlock it
|
||||||
|
/* outb(0x87, sio->port);
|
||||||
|
outb(0x87, sio->port);
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
exit_pnp(struct superio *sio)
|
||||||
|
{
|
||||||
|
// The 87351 dosen't seem to need this
|
||||||
|
|
||||||
|
/* all done. */
|
||||||
|
// select configure control
|
||||||
|
/*
|
||||||
|
outb(0xaa, sio->port);
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
||||||
|
static void write_config(struct superio *sio,
|
||||||
|
unsigned char value, unsigned char reg)
|
||||||
|
{
|
||||||
|
outb(reg, sio->port);
|
||||||
|
outb(value, sio->port +1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned char read_config(struct superio *sio, unsigned char reg)
|
||||||
|
{
|
||||||
|
outb(reg, sio->port);
|
||||||
|
return inb(sio->port +1);
|
||||||
|
}
|
||||||
|
static void set_logical_device(struct superio *sio, int device)
|
||||||
|
{
|
||||||
|
write_config(sio, device, 0x07);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_irq0(struct superio *sio, unsigned irq)
|
||||||
|
{
|
||||||
|
write_config(sio, irq, 0x70);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_irq1(struct superio *sio, unsigned irq)
|
||||||
|
{
|
||||||
|
write_config(sio, irq, 0x72);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_drq(struct superio *sio, unsigned drq)
|
||||||
|
{
|
||||||
|
write_config(sio, drq & 0xff, 0x74);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_iobase0(struct superio *sio, unsigned iobase)
|
||||||
|
{
|
||||||
|
write_config(sio, (iobase >> 8) & 0xff, 0x60);
|
||||||
|
write_config(sio, iobase & 0xff, 0x61);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_iobase1(struct superio *sio, unsigned iobase)
|
||||||
|
{
|
||||||
|
write_config(sio, (iobase >> 8) & 0xff, 0x62);
|
||||||
|
write_config(sio, iobase & 0xff, 0x63);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static void set_enable(struct superio *sio, int enable)
|
||||||
|
{
|
||||||
|
write_config(sio, enable?0x1:0x0, 0x30);
|
||||||
|
#if 1
|
||||||
|
if (enable) {
|
||||||
|
printk_debug("enabled superio device: %d\n",
|
||||||
|
read_config(sio, 0x07));
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_mux_pins(struct superio *sio, unsigned char val)
|
||||||
|
{
|
||||||
|
write_config(sio,val,0x22);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_conf3(struct superio *sio, unsigned char val)
|
||||||
|
{
|
||||||
|
write_config(sio,val,0x23);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_parallel(struct superio *sio)
|
||||||
|
{
|
||||||
|
/* Remember the default resources */
|
||||||
|
unsigned iobase = PARALLEL_DEFAULT_IOBASE;
|
||||||
|
unsigned irq = PARALLEL_DEFAULT_IRQ;
|
||||||
|
unsigned drq = PARALLEL_DEFAULT_DRQ;
|
||||||
|
/* Select the device */
|
||||||
|
set_logical_device(sio, PARALLEL_DEVICE);
|
||||||
|
/* Disable it while initializing */
|
||||||
|
set_enable(sio, 0);
|
||||||
|
if (sio->lpt) {
|
||||||
|
set_iobase0(sio, iobase);
|
||||||
|
set_irq0(sio, irq);
|
||||||
|
set_drq(sio, drq);
|
||||||
|
set_enable(sio, 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// test a non-fifo uart init. Stupid chip.
|
||||||
|
/* Line Control Settings */
|
||||||
|
#ifndef TTYS0_LCS
|
||||||
|
/* Set 8bit, 1 stop bit, no parity */
|
||||||
|
#define TTYS0_LCS 0x3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define UART_LCS TTYS0_LCS
|
||||||
|
|
||||||
|
/* Data */
|
||||||
|
#define UART_RBR 0x00
|
||||||
|
#define UART_TBR 0x00
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Control */
|
||||||
|
#define UART_IER 0x01
|
||||||
|
#define UART_IIR 0x02
|
||||||
|
#define UART_FCR 0x02
|
||||||
|
#define UART_LCR 0x03
|
||||||
|
#define UART_MCR 0x04
|
||||||
|
#define UART_DLL 0x00
|
||||||
|
#define UART_DLM 0x01
|
||||||
|
|
||||||
|
/* Status */
|
||||||
|
#define UART_LSR 0x05
|
||||||
|
#define UART_MSR 0x06
|
||||||
|
#define UART_SCR 0x07
|
||||||
|
|
||||||
|
inline void uart_init_nofifo(unsigned base_port, unsigned divisor)
|
||||||
|
{
|
||||||
|
/* disable interrupts */
|
||||||
|
outb(0x0, base_port + UART_IER);
|
||||||
|
#if 0
|
||||||
|
/* enable fifo's */
|
||||||
|
outb(0x01, base_port + UART_FCR);
|
||||||
|
#else
|
||||||
|
outb(0x06, base_port + UART_FCR);
|
||||||
|
#endif
|
||||||
|
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
|
||||||
|
outb(0x80 | UART_LCS, base_port + UART_LCR);
|
||||||
|
outb(divisor & 0xFF, base_port + UART_DLL);
|
||||||
|
outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
|
||||||
|
outb(UART_LCS, base_port + UART_LCR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
static void setup_com(struct superio *sio,
|
||||||
|
struct com_ports *com, int device)
|
||||||
|
{
|
||||||
|
// set baud, default to 115200 if not set.
|
||||||
|
int divisor = 115200/(com->baud ? com->baud : 1);
|
||||||
|
printk_debug("%s com device: %02x\n",
|
||||||
|
com->enable? "Enabling" : "Disabling", device);
|
||||||
|
/* Select the device */
|
||||||
|
set_logical_device(sio, device);
|
||||||
|
/* Disable it while it is initialized */
|
||||||
|
set_enable(sio, 0);
|
||||||
|
|
||||||
|
if (com->enable) {
|
||||||
|
printk_debug(" iobase = 0x%04x irq=%d\n",
|
||||||
|
com->base, com->irq);
|
||||||
|
set_iobase0(sio, com->base);
|
||||||
|
set_irq0(sio, com->irq);
|
||||||
|
/* We are initialized so enable the device */
|
||||||
|
set_enable(sio, 1);
|
||||||
|
/* Now initialize the com port */
|
||||||
|
uart_init(com->base, divisor);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void setup_floppy(struct superio *sio)
|
||||||
|
{
|
||||||
|
/* Remember the default resources */
|
||||||
|
unsigned iobase = FLOPPY_DEFAULT_IOBASE;
|
||||||
|
unsigned irq = FLOPPY_DEFAULT_IRQ;
|
||||||
|
unsigned drq = FLOPPY_DEFAULT_DRQ;
|
||||||
|
/* Select the device */
|
||||||
|
set_logical_device(sio, FLOPPY_DEVICE);
|
||||||
|
/* Disable it while initializing */
|
||||||
|
set_enable(sio, 0);
|
||||||
|
if (sio->floppy) {
|
||||||
|
set_iobase0(sio, iobase);
|
||||||
|
set_irq0(sio, irq);
|
||||||
|
set_drq(sio, drq);
|
||||||
|
set_enable(sio, 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if NO_KEYBOARD==0
|
||||||
|
|
||||||
|
void pc_keyboard_init();
|
||||||
|
|
||||||
|
static void setup_keyboard(struct superio *sio)
|
||||||
|
{
|
||||||
|
/* Remember the default resources */
|
||||||
|
unsigned iobase0 = KBC_DEFAULT_IOBASE0;
|
||||||
|
unsigned iobase1 = KBC_DEFAULT_IOBASE1;
|
||||||
|
unsigned irq0 = KBC_DEFAULT_IRQ0;
|
||||||
|
/* Select the device */
|
||||||
|
set_logical_device(sio, KBC_DEVICE);
|
||||||
|
/* Disable it while initializing */
|
||||||
|
set_enable(sio, 0);
|
||||||
|
if (sio->keyboard) {
|
||||||
|
set_iobase0(sio, iobase0);
|
||||||
|
set_iobase1(sio, iobase1);
|
||||||
|
set_irq0(sio, irq0);
|
||||||
|
set_enable(sio, 1);
|
||||||
|
/* Initialize the keyboard */
|
||||||
|
pc_keyboard_init();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ENABLE_MOUSE==1
|
||||||
|
static void setup_mouse(struct superio *sio)
|
||||||
|
{
|
||||||
|
/* Remember the default resources */
|
||||||
|
unsigned irq0 = MOUSE_DEFAULT_IRQ0;
|
||||||
|
/* Select the device */
|
||||||
|
set_logical_device(sio, MOUSE_DEVICE);
|
||||||
|
/* Disable it while initializing */
|
||||||
|
set_enable(sio, 0);
|
||||||
|
if (sio->mouse) {
|
||||||
|
set_irq0(sio, irq0);
|
||||||
|
set_enable(sio, 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void setup_devices(struct superio *sio)
|
||||||
|
{
|
||||||
|
if (sio->port == 0) {
|
||||||
|
sio->port = sio->super->defaultport;
|
||||||
|
}
|
||||||
|
if (sio->com1.base == 0) sio->com1.base = COM1_DEFAULT_IOBASE;
|
||||||
|
if (sio->com1.irq == 0) sio->com1.irq = COM1_DEFAULT_IRQ;
|
||||||
|
if (sio->com1.baud == 0) sio->com1.baud = COM1_DEFAULT_BAUD;
|
||||||
|
if (sio->com2.base == 0) sio->com2.base = COM2_DEFAULT_IOBASE;
|
||||||
|
if (sio->com2.irq == 0) sio->com2.irq = COM2_DEFAULT_IRQ;
|
||||||
|
if (sio->com2.baud == 0) sio->com2.baud = COM2_DEFAULT_BAUD;
|
||||||
|
|
||||||
|
enter_pnp(sio);
|
||||||
|
|
||||||
|
/* setup pins to be IRQ1, 3-7 and 12.
|
||||||
|
Default is to enable PCICLK and SERIRQ and GPIO.
|
||||||
|
Bits7-1 = Default;
|
||||||
|
Bit0 = 0; Default = 1;
|
||||||
|
*/
|
||||||
|
set_mux_pins(sio,0xa0);
|
||||||
|
|
||||||
|
/* setup more pin mux options */
|
||||||
|
set_conf3(sio,0x01);
|
||||||
|
|
||||||
|
/* enable/disable floppy */
|
||||||
|
setup_floppy(sio);
|
||||||
|
|
||||||
|
/* enable or disable parallel */
|
||||||
|
setup_parallel(sio);
|
||||||
|
|
||||||
|
/* enable/disable com1 */
|
||||||
|
setup_com(sio, &sio->com1, COM1_DEVICE);
|
||||||
|
|
||||||
|
/* enable/disable com2 */
|
||||||
|
setup_com(sio, &sio->com2, COM2_DEVICE);
|
||||||
|
|
||||||
|
#if ENABLE_MOUSE==1
|
||||||
|
setup_mouse(sio);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if NO_KEYBOARD==0
|
||||||
|
/* enable/disable keyboard */
|
||||||
|
setup_keyboard(sio);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* // gpio_port2
|
||||||
|
set_logical_device(sio, GPIO_PORT2_DEVICE);
|
||||||
|
set_enable(sio, sio->gpio2);
|
||||||
|
|
||||||
|
// gpio_port3
|
||||||
|
set_logical_device(sio, GPIO_PORT3_DEVICE);
|
||||||
|
set_enable(sio, sio->gpio3);
|
||||||
|
*/
|
||||||
|
|
||||||
|
exit_pnp(sio);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef USE_NEW_SUPERIO_INTERFACE
|
||||||
|
|
||||||
|
// this must die soon.
|
||||||
|
void
|
||||||
|
final_superio_fixup()
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
static struct superio temp = { &superio_NSC_pc87351_control,
|
||||||
|
.com1={1}, .floppy=1};
|
||||||
|
finishup(&temp);
|
||||||
|
|
||||||
|
enable_com(PNP_COM1_DEVICE);
|
||||||
|
enable_com(PNP_COM2_DEVICE);
|
||||||
|
|
||||||
|
exit_pnp();
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
#endif
|
||||||
54
util/config/bitworks_ims-440bx.config
Normal file
54
util/config/bitworks_ims-440bx.config
Normal file
|
|
@ -0,0 +1,54 @@
|
||||||
|
target src
|
||||||
|
mainboard bitworks/ims
|
||||||
|
|
||||||
|
option CONFIGURE_L2_CACHE=1
|
||||||
|
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
|
||||||
|
|
||||||
|
option SERIAL_CONSOLE=1
|
||||||
|
option DEFAULT_CONSOLE_LEVEL=9
|
||||||
|
option MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||||
|
|
||||||
|
option RAMTEST=0
|
||||||
|
#option ROM_IMAGE_SIZE=327680
|
||||||
|
#option ROM_IMAGE_SIZE=393216
|
||||||
|
|
||||||
|
option NO_KEYBOARD=0
|
||||||
|
option ENABLE_MOUSE=1
|
||||||
|
|
||||||
|
# This option controls if the Native IDE code attempts to run
|
||||||
|
option BOOT_IDE=0
|
||||||
|
|
||||||
|
option CONFIG_COMPRESS=0
|
||||||
|
|
||||||
|
option USE_GENERIC_ROM=1
|
||||||
|
|
||||||
|
option USE_ELF_BOOT=1
|
||||||
|
|
||||||
|
option CONFIG_ASSIGNIRQ=1
|
||||||
|
|
||||||
|
# Etherboot IDE driver
|
||||||
|
#option PAYLOAD_SIZE=32768
|
||||||
|
#payload /bitworks/src/etherboot-5.1.8/src/bin/ide_disk.zelf
|
||||||
|
|
||||||
|
# ADLO
|
||||||
|
# linuxbios rom size. Should be 512k-*actual* size of payload
|
||||||
|
option ROM_IMAGE_SIZE=360448
|
||||||
|
# remember this is not absolute but just the dd bs=parameter
|
||||||
|
# so it can be larger than what you have specified
|
||||||
|
#
|
||||||
|
option PAYLOAD_SIZE=32768
|
||||||
|
payload /bitworks/src/freebios/util/ADLO/payload
|
||||||
|
|
||||||
|
# Memtest size is larger than I need but I like powers of 2
|
||||||
|
#option PAYLOAD_SIZE=131072
|
||||||
|
#payload /bitworks/src/memtest86-3.0/memtest
|
||||||
|
|
||||||
|
#option VIDEO_CONSOLE=1
|
||||||
|
#option CONFIG_PCIBIOS=1
|
||||||
|
#option CONFIG_VGABIOS=1
|
||||||
|
#option CONFIG_REALMODE_IDT=1
|
||||||
|
|
||||||
|
#option CONFIG_ENABLE_MOUSE_IRQ12=1
|
||||||
|
|
||||||
|
makerule tonet: linuxbios.rom ;
|
||||||
|
addaction romimage ./2net
|
||||||
Loading…
Add table
Reference in a new issue