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UPSTREAM: soc/intel/skylake: Add option to enable/disable EIST

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Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

BUG=none
BRANCH=none
TEST=none

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 6b45ee44a9
Original-Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19676
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I4f42dfaab44c82e82254ca51d963e06b771d9dd3
Reviewed-on: https://chromium-review.googlesource.com/506904
This commit is contained in:
Subrata Banik 2017-05-12 11:43:57 +05:30 • committed by chrome-bot
parent 3138a60d48
commit 3e985d3aad
4 changed files with 19 additions and 4 deletions
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7
src/soc/intel/skylake/acpi.c
View file

@ -523,9 +523,10 @@ void generate_cpu_entries(device_t device)
generate_c_state_entries(is_s0ix_enable,
max_c_state);
/* Generate P-state tables */
generate_p_state_entries(core_id,
cores_per_package);
if (config->eist_enable)
/* Generate P-state tables */
generate_p_state_entries(core_id,
cores_per_package);
acpigen_pop_len();
}

6
src/soc/intel/skylake/chip.h
View file

@ -459,6 +459,12 @@ struct soc_intel_skylake_config {
/* Enable SGX feature */
u8 sgx_enable;
/* Enable/Disable EIST
* 1b - Enabled
* 0b - Disabled
*/
u8 eist_enable;
};
typedef struct soc_intel_skylake_config config_t;

3
src/soc/intel/skylake/chip_fsp20.c
View file

@ -261,6 +261,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Enable PMC XRAM read */
tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
/* Enable/Disable EIST */
tconfig->Eist = config->eist_enable;
soc_irq_settings(params);
}

7
src/soc/intel/skylake/cpu.c
View file

@ -245,12 +245,17 @@ static void configure_isst(void)
static void configure_misc(void)
{
device_t dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
if (conf->eist_enable)
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
else
msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */