mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
haswell: Fix monotonic timer integration
In some previous attempt to enable monotonic timers on all platforms, the LAPIC monotonic timer was selected for Haswell devices, despite the fact that LAPIC timers are not used in coreboot on Haswell (See haswell Kconfig) and there already was a monotonic timer implementation enabled that just needed to be added for SMM as well. Change-Id: I6beb2977864e507956636860ed463e1991cea1ed Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8702 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
parent
c3d15a7210
commit
3d78ece7d0
2 changed files with 1 additions and 1 deletions
|
@ -25,7 +25,6 @@ config CPU_SPECIFIC_OPTIONS
|
|||
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
|
||||
select PARALLEL_CPU_INIT
|
||||
select PARALLEL_MP
|
||||
select LAPIC_MONOTONIC_TIMER
|
||||
|
||||
config BOOTBLOCK_CPU_INIT
|
||||
string
|
||||
|
|
|
@ -11,5 +11,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
|
|||
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
|
||||
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
|
||||
smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
|
||||
|
||||
cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
|
||||
|
|
Loading…
Add table
Reference in a new issue