Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

This patch fixes up kontron for the new resource allocator. More

Browse source 
could be done.
	
northbridge/intel/i945/northbridge.dts
	Remove bridge flag.  Northbridges don't have children.  The domains
	they implement do.
northbridge/intel/i945/northbridge.c
	Add IORESOURCE_BRIDGE flags and change the limit for MMIO to avoid ROM.
mainboard/kontron/986lcd-m/dts
	Make PCI devices children of the domain and add a few devices.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1093 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Myles Watson 2008-12-31 20:02:03 +00:00
parent 267ce7cbf7
commit 3c6580c888
3 changed files with 90 additions and 53 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

131
mainboard/kontron/986lcd-m/dts
View file

@ -145,55 +145,90 @@ end
};
domain@0 {
/config/("northbridge/intel/i945/northbridge.dts");
/* guesses; we need a real lspci */
pci@0,0 {
pci@1b,0 {
/config/("southbridge/intel/i82801gx/ac97audio.dts");
};
pci@1c,0 {
/config/("southbridge/intel/i82801gx/pcie1.dts");
};
pci@1c,1 {
/config/("southbridge/intel/i82801gx/pcie2.dts");
};
pci@1c,2{
/config/("southbridge/intel/i82801gx/pcie3.dts");
};
pci@1d,0{
/config/("southbridge/intel/i82801gx/usb1.dts");
};
pci@1d,1{
/config/("southbridge/intel/i82801gx/usb2.dts");
};
pci@1d,2{
/config/("southbridge/intel/i82801gx/usb3.dts");
};
pci@1d,3{
/config/("southbridge/intel/i82801gx/usb4.dts");
};
pci@1d,7{
/config/("southbridge/intel/i82801gx/usb_ehci.dts");
};
pci@1e,0{
/config/("southbridge/intel/i82801gx/pci.dts");
};
pci@1f,0{/* which ich? */
/config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts");
};
pci@1f,1{
/config/("southbridge/intel/i82801gx/ide.dts");
};
pci@1f,2{
/config/("southbridge/intel/i82801gx/sata.dts");
};
pci@1f,3{
/config/("southbridge/intel/i82801gx/smbus.dts");
};
pci@0,0 {
/config/("northbridge/intel/i945/mc.dts");
};
ioport@2e {
/config/("superio/winbond/w83627thg/dts");
com1enable = "1";
pci@1,0 { /* PCIe */
disabled;
};
pci@2,0 { /* Onboard VGA. */
rom_address = "0xfff00000"; /* Shouldn't this be a lar path? */
};
pci@2,1 { /* Display controller. */
};
pci@1b,0 {
/config/("southbridge/intel/i82801gx/ac97audio.dts");
};
pci@1c,0 {
/config/("southbridge/intel/i82801gx/pcie1.dts");
};
pci@1c,1 {
/config/("southbridge/intel/i82801gx/pcie2.dts");
};
pci@1c,2{
/config/("southbridge/intel/i82801gx/pcie3.dts");
};
pci@1c,3{ disabled; }; /* PCIe port 4 */
pci@1c,4{ disabled; }; /* PCIe port 5 */
pci@1c,5{ disabled; }; /* PCIe port 6 */
pci@1d,0{
/config/("southbridge/intel/i82801gx/usb1.dts");
};
pci@1d,1{
/config/("southbridge/intel/i82801gx/usb2.dts");
};
pci@1d,2{
/config/("southbridge/intel/i82801gx/usb3.dts");
};
pci@1d,3{
/config/("southbridge/intel/i82801gx/usb4.dts");
};
pci@1d,7{
/config/("southbridge/intel/i82801gx/usb_ehci.dts");
};
pci@1e,0{
/config/("southbridge/intel/i82801gx/pci.dts");
};
pci@1e,2{ disabled; }; /* AC'97 Audio */
pci@1e,3{ disabled; }; /* AC'97 Modem */
pci@1f,0{/* which ich? */
/config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts");
ioport@2e {
/config/("superio/winbond/w83627thg/dts");
com1enable = "1";
com2enable = "1";
kbenable = "1";
/* irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq */
gameenable = "1";
gpio2enable = "1";
gpio34enable = "1";
hwmenable = "1";
};
ioport@4e {
/config/("superio/winbond/w83627thg/dts");
com1enable = "1";
com1io = "0x3e8";
com1irq = "11";
com2enable = "1";
com2io = "0x2e8";
com2irq = "10";
};
};
pci@1f,1{ /* Disabled and commented out in v2. */
/config/("southbridge/intel/i82801gx/ide.dts");
disabled;
};
pci@1f,2{
/config/("southbridge/intel/i82801gx/sata.dts");
};
pci@1f,3{
/config/("southbridge/intel/i82801gx/smbus.dts");
};
/* Disabled and commented out in v2.
* pci@1f,4{
* /config/("southbridge/intel/i82801gx/codec.dts");
* disabled;
* };
*/
};
};

11
northbridge/intel/i945/northbridge.c
View file

@ -51,8 +51,8 @@ static void I945_pci_domain_read_resources(struct device * dev)
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_BRIDGE;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
@ -60,9 +60,10 @@ static void I945_pci_domain_read_resources(struct device * dev)
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffffffUL;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* This is a hack. I don't know all the right reserved regions. */
resource->limit = 0xfeffffffUL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_BRIDGE;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)

1
northbridge/intel/i945/northbridge.dts
View file

@ -19,4 +19,5 @@
*/
{
device_operations = "i945_pci_domain_ops";
bridge;
};