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UPSTREAM: arch/riscv: Add misc.c to bootblock/romstage to get udelay()

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The uart8250mem driver needs it.

BUG=None
BRANCH=None
TEST=None

Change-Id: I09e6a17cedf8a4045f008f5a0d225055d745e8db
Original-Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Original-Reviewed-on: https://review.coreboot.org/15147
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352024
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-06-10 19:35:15 +02:00 • committed by chrome-bot
parent 09e2cb8296
commit 3c17c59bb4
1 changed files with 2 additions and 0 deletions
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2
src/arch/riscv/Makefile.inc
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@ -34,6 +34,7 @@ bootblock-y += trap_handler.c
bootblock-y += virtual_memory.c
bootblock-y += boot.c
bootblock-y += rom_media.c
bootblock-y += misc.c
bootblock-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \
@ -57,6 +58,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
romstage-y += boot.c
romstage-y += stages.c
romstage-y += rom_media.c
romstage-y += misc.c
romstage-y += \
$(top)/src/lib/memchr.c \
$(top)/src/lib/memcmp.c \