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Add support for Cache-as-RAM on VIA C7 processors in v3.
This required lots of preparatory work to not make the existing stage0
situation worse.
Thanks to Jason Zhao we got a skeleton CAR code for VIA C7 based on
older v2 code.
I cleaned it up, modified it to fit into the improved v3 stage0 code
infrastructure and believe this is mostly merge-ready.
Thanks to Bari Ari for getting the code to me for rewrite/review.
Thanks to Corey Osgood who kept me going with helpful early tests and
motivation.
Thanks to everybody who reviewed my code.
CONFIG_CARTEST shall not be enabled (breaks the build).
CONFIG_XIP_ROM_{SIZE,BASE} shall not be set (breaks the build).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@915 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger
parent
8647942e82
commit
3bb18f8a3c
3 changed files with 223 additions and 0 deletions
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@ -56,6 +56,15 @@ config CPU_AMD_K8
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_VIA_C7
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CONFIG_HPET
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boolean
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depends CPU_AMD_K8
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@ -159,6 +168,7 @@ config CARBASE
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default 0x8f000 if CPU_I586
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default 0x80000 if CPU_AMD_GEODELX
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default 0xc8000 if CPU_AMD_K8
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default 0xffef0000 if CPU_VIA_C7
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help
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This option sets the base address of the area used for CAR.
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@ -167,6 +177,7 @@ config CARSIZE
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default 0x1000 if CPU_I586
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default 0x8000 if CPU_AMD_GEODELX
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default 0x8000 if CPU_AMD_K8
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default 0x8000 if CPU_VIA_C7
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help
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This option sets the size of the area used for CAR.
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@ -175,6 +186,7 @@ config CBMEMK
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default 0x1000 if CPU_I586
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default 0x1000 if CPU_AMD_GEODELX
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default 0x2000 if CPU_AMD_K8
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default 0x1000 if CPU_VIA_C7
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help
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This option sets the top of the memory area, in KiB,
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used for coreboot.
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@ -122,6 +122,10 @@ else
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ifeq ($(CONFIG_CPU_AMD_K8),y)
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STAGE0_CAR_OBJ = amd/stage0.o
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STAGE0_ARCH_X86_SRC += amd/k8/stage1.c
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else
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ifeq ($(CONFIG_CPU_VIA_C7),y)
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STAGE0_CAR_OBJ = via/stage0.o
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endif
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endif
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endif
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endif
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207
arch/x86/via/stage0.S
Normal file
207
arch/x86/via/stage0.S
Normal file
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@ -0,0 +1,207 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2005 Eswar Nallusamy, LANL
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* Copyright (C) 2005 Tyan
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* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
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* Copyright (C) 2007 coresystems GmbH
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* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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* Copyright (C) 2007,2008 Carl-Daniel Hailfinger
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* Copyright (C) 2008 VIA Technologies, Inc.
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* (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
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#include <macros.h>
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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.align 4
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.globl protected_stage0
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protected_stage0:
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/* This code was used by v2. TODO. */
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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.globl __protected_stage0
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__protected_stage0:
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/* Save the BIST result. */
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movl %eax, %ebp
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port80_post(0x01)
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax. */
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movl %ebp, %eax
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.align 4
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#define CacheSize CONFIG_CARSIZE
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#define CacheBase CONFIG_CARBASE
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#define ASSEMBLY
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#include <mtrr.h>
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/* Save the BIST result */
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movl %eax, %ebp
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CacheAsRam:
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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movl %eax,%cr0
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invd
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* MTRRPhysBase */
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x201, %ecx
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/* This assumes we never access addresses above 2^36 in CAR. */
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movl $0x0000000f,%edx
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movl $(~(CacheSize-1)|0x800),%eax
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wrmsr
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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/* MTRRPhysBase */
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax
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wrmsr
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/* MTRRPhysMask */
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movl $0x203, %ecx
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movl $0x0000000f,%edx
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000800, %eax
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wrmsr
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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/* Read the range with lodsl */
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movl $CacheBase, %esi
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cld
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
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/* Read the XIP area */
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movl XIP_ROM_BASE, %esi
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movl $(XIP_ROM_SIZE>>2), %ecx
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rep lodsl
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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/* The key point of this CAR code is C7 cache does not turn into
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* "no fill" mode, which is not compatible with general CAR code.
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*/
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/* set up the stack pointer */
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movl $(CacheBase + CacheSize - 4), %eax
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movl %eax, %esp
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/* Load a different set of data segments */
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movw $CACHE_RAM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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lout:
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/* Store zero for the pointer to the global variables. */
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pushl $0
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/* Restore the BIST result. */
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movl %ebp, %eax
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/* We need to set ebp? No need. */
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movl %esp, %ebp
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/* Second parameter: init_detected */
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/* Store zero for the unused init_detected parameter. */
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pushl $0
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/* First parameter: bist */
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pushl %eax
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call stage1_main
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/* We will not go back. */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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#include "../stage0_common.S"
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