Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: intel car: Remove guard on XIP_ROM_SIZE

Browse source 
These guards have been removed starting with model_206ax.

BUG=None
BRANCH=None
TEST=None

Change-Id: Id63034ec4080e37eee2c120aa1f1ef604db5b203
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/15758
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362684
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-20 13:31:00 +03:00 • committed by chrome-bot
parent 020298dca6
commit 39a1aa9833
3 changed files with 0 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/cpu/intel/car/cache_as_ram.inc
View file

@ -225,8 +225,6 @@ clear_fixed_var_mtrr_out:
simplemask CacheSize, 0 simplemask CacheSize, 0
wrmsr wrmsr
#if CONFIG_XIP_ROM_SIZE
/* /*
* Enable write base caching so we can do execute in place (XIP) * Enable write base caching so we can do execute in place (XIP)
* on the flash ROM. * on the flash ROM.
@ -246,7 +244,6 @@ clear_fixed_var_mtrr_out:
movl $0x0000000f, %edx movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax

2
src/cpu/intel/car/cache_as_ram_ht.inc
View file

@ -302,7 +302,6 @@ no_msr_11e:
post_code(0x2d) post_code(0x2d)
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
@ -319,7 +318,6 @@ no_msr_11e:
rdmsr rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax

2
src/cpu/intel/model_6ex/cache_as_ram.inc
View file

@ -96,7 +96,6 @@ clear_mtrrs:
orl $CR0_CacheDisable, %eax orl $CR0_CacheDisable, %eax
movl %eax, %cr0 movl %eax, %cr0
#if CONFIG_XIP_ROM_SIZE
/* Enable cache for our code in Flash because we do XIP here */ /* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
@ -113,7 +112,6 @@ clear_mtrrs:
movl $CPU_PHYSMASK_HI, %edx movl $CPU_PHYSMASK_HI, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
#endif /* CONFIG_XIP_ROM_SIZE */
/* Enable cache. */ /* Enable cache. */
movl %cr0, %eax movl %cr0, %eax