mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
initial checkin for vt8235
This commit is contained in:
Andrew Ip
parent
f46a929825
commit
398b287d09
4 changed files with 346 additions and 0 deletions
1
src/southbridge/via/vt8235/Config
Normal file
1
src/southbridge/via/vt8235/Config
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object southbridge.o
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14
src/southbridge/via/vt8235/setup_ethernet.inc
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14
src/southbridge/via/vt8235/setup_ethernet.inc
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/*
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* This early setup is a handy place to enable the Ethernet if the user wants
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* it.
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*/
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enable_eth:
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movl $CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax
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PCI_READ_CONFIG_DWORD
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/* Turn on just the Ethernet and disable modem */
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orl $0x1080, %eax
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mov %eax, %ecx
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movl $CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax
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PCI_WRITE_CONFIG_DWORD
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28
src/southbridge/via/vt8235/setup_ide.inc
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28
src/southbridge/via/vt8235/setup_ide.inc
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config_ide:
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movl $CONFIG_ADDR(0, 0x88, 0x50), %eax
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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movl $CONFIG_ADDR(0, 0x89, 0x04), %eax
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movb $0x07, %dl
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PCI_WRITE_CONFIG_BYTE
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movl $CONFIG_ADDR(0, 0x89, 0x40), %eax
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movb $0x03, %dl
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PCI_WRITE_CONFIG_BYTE
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// This early setup switches IDE into compatibility mode before PCI gets
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// a chance to assign I/Os
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#if (!ENABLE_IDE_NATIVE_MODE)
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movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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movl $CONFIG_ADDR(0, 0x89, 0x3c), %eax
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movb $0x0e, %dl
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PCI_WRITE_CONFIG_BYTE
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movl $CONFIG_ADDR(0, 0x89, 0x3d), %eax
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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#endif
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303
src/southbridge/via/vt8235/southbridge.c
Normal file
303
src/southbridge/via/vt8235/southbridge.c
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#include <pci.h>
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#include <pc80/keyboard.h>
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#include <pc80/mc146818rtc.h>
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#include <printk.h>
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#include <pci_ids.h>
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#include <arch/io.h>
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// #define IDE_NATIVE_MODE 1
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void usb_on()
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{
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unsigned char regval;
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/* Base 8235 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
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0x3177, 0);
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/* USB controller 1 */
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struct pci_dev *dev1 = pci_find_device(PCI_VENDOR_ID_VIA, \
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0x3038, 0);
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/* USB controller 2 */
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struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \
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0x3038, \
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dev1);
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/* USB controller 3 */
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struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \
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0x3038, \
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dev2);
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#if ENABLE_VT8235_USB
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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regval &= ~(0x36);
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pci_write_config_byte(dev0, 0x50, regval);
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}
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/* enable USB1 */
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if(dev1) {
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pci_write_config_byte(dev1, 0x3c, 0x05);
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pci_write_config_byte(dev1, 0x04, 0x07);
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}
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/* enable USB2 */
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if(dev2) {
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pci_write_config_byte(dev2, 0x3c, 0x05);
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pci_write_config_byte(dev2, 0x04, 0x07);
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}
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/* enable USB3 */
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if(dev3) {
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pci_write_config_byte(dev3, 0x3c, 0x05);
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pci_write_config_byte(dev3, 0x04, 0x07);
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}
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#else
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
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regval |= 0x36;
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pci_write_config_byte(dev0, 0x50, regval);
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}
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/* disable USB1 */
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if(dev1) {
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pci_write_config_byte(dev1, 0x3c, 0x00);
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pci_write_config_byte(dev1, 0x04, 0x00);
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}
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/* disable USB2 */
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if(dev2) {
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pci_write_config_byte(dev2, 0x3c, 0x00);
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pci_write_config_byte(dev2, 0x04, 0x00);
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}
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/* disable USB3 */
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if(dev3) {
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pci_write_config_byte(dev3, 0x3c, 0x00);
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pci_write_config_byte(dev3, 0x04, 0x00);
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}
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#endif
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}
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void keyboard_on()
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{
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unsigned char regval;
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/* Base 8235 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
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0x3177, 0);
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if (dev0) {
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pci_read_config_byte(dev0, 0x51, ®val);
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// regval |= 0x0f;
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/* !!!FIX let's try this */
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regval |= 0x1d;
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pci_write_config_byte(dev0, 0x51, regval);
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}
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pc_keyboard_init();
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}
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void nvram_on()
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{
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}
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/*
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* Enable the ethernet device and turn off stepping (because it is integrated
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* inside the southbridge)
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*/
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void ethernet_fixup()
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{
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struct pci_dev *dev, *edev;
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u8 byte;
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printk_info("Ethernet fixup\n");
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edev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3065, 0);
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if (edev != NULL) {
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printk_debug("Configuring VIA LAN\n");
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/* We don't need stepping - though the device supports it */
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pci_read_config_byte(edev, PCI_COMMAND, &byte);
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byte &= ~PCI_COMMAND_WAIT;
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pci_write_config_byte(edev, PCI_COMMAND, byte);
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/* turn on master and pio */
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pci_read_config_byte(edev, PCI_COMMAND, &byte);
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byte = byte | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
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pci_write_config_byte(edev, PCI_COMMAND, byte);
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} else {
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printk_debug("VIA LAN not found\n");
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}
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}
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void southbridge_fixup()
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{
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unsigned char enables;
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struct pci_dev *dev0;
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struct pci_dev *dev1;
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struct pci_dev *devpwr;
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/* Base 8235 controller */
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dev0 = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
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/* IDE controller */
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dev1 = pci_find_device(PCI_VENDOR_ID_VIA, 0x0571, 0);
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/* follow award */
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enables = pci_read_config_byte(dev0, 0x6C, &enables);
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enables = 0x00;
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pci_write_config_byte(dev0, 0x6C, enables);
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/* Map 4MB of FLASH into the address space */
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pci_write_config_byte(dev0, 0x41, 0x7f);
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/*
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* Set bit 6 of 0x40, because Award does it (IO recovery time)
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* IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
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* interrupts can be properly marked as level triggered.
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*/
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enables = pci_read_config_byte(dev0, 0x40, &enables);
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enables |= 0x45;
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pci_write_config_byte(dev0, 0x40, enables);
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/* Set 0x42 to 0xf0 to match Award bios */
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enables = pci_read_config_byte(dev0, 0x42, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev0, 0x42, enables);
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/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
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enables = pci_read_config_byte(dev0, 0x4f, &enables);
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enables |= 0x08;
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pci_write_config_byte(dev0, 0x4f, enables);
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/* Set 0x58 to 0x03 to match Award */
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pci_write_config_byte(dev0, 0x58, 0x03);
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#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS
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/* enable com1 and com2. */
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enables = pci_read_config_byte(dev0, 0x6e, &enables);
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/*
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* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 is enable
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* com port a as com1
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*/
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/* following award */
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enables = 0x00;
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pci_write_config_byte(dev0, 0x6e, enables);
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/*
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* note: this is also a redo of some port of assembly, but we want
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* everything up.
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* set com1 to 115 kbaud
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* not clear how to do this yet.
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* forget it; done in assembly.
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*/
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#endif
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/*
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* enable IDE, since Linux won't do it.
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* First do some more things to devfn (17,0)
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* note: this should already be cleared, according to the book.
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*/
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pci_read_config_byte(dev0, 0x50, &enables);
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printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
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enables &= ~8; // need manifest constant here!
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printk_debug("set IDE reg. 50 to 0x%x\n", enables);
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pci_write_config_byte(dev0, 0x50, enables);
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/* enable serial irq */
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pci_write_config_byte(dev0, 0x52, 0x09);
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/* dma */
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pci_write_config_byte(dev0, 0x53, 0x00);
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/* diskable dynamic clock stop */
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pci_write_config_byte(dev0, 0x5b, 0x00);
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/*
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* IDE setup
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*/
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#if !(ENABLE_IDE_NATIVE_MODE)
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/*
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* Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
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* interrupts. Using PCI ints confuses linux for some reason.
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*/
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pci_read_config_byte(dev1, 0x42, &enables);
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printk_debug("enables in reg 0x42 0x%x\n", enables);
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enables &= ~0xc0;
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pci_write_config_byte(dev1, 0x42, enables);
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pci_read_config_byte(dev1, 0x42, &enables);
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printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
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#endif
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pci_read_config_byte(dev1, 0x40, &enables);
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printk_debug("enables in reg 0x40 0x%x\n", enables);
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enables |= 3;
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pci_write_config_byte(dev1, 0x40, enables);
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pci_read_config_byte(dev1, 0x40, &enables);
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printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
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/* Enable prefetch buffers */
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pci_read_config_byte(dev1, 0x41, &enables);
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enables |= 0xf0;
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pci_write_config_byte(dev1, 0x41, enables);
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/* Lower thresholds (cause award does it) */
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pci_read_config_byte(dev1, 0x43, &enables);
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enables &= ~0x0f;
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enables |= 0x05;
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pci_write_config_byte(dev1, 0x43, enables);
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/* PIO read prefetch counter (cause award does it) */
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pci_write_config_byte(dev1, 0x44, 0x18);
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/* Use memory read multiple */
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pci_write_config_byte(dev1, 0x45, 0x1c);
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/* address decoding. */
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pci_read_config_byte(dev1, 0x9, &enables);
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printk_debug("enables in reg 0x9 0x%x\n", enables);
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/* by the book, set the low-order nibble to 0xa. */
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#if ENABLE_IDE_NATIVE_MODE
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enables &= ~0xf;
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/* cf/cg silicon needs an 'f' here. */
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enables |= 0xf;
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#else
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enables &= ~0x5;
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#endif
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pci_write_config_byte(dev1, 0x9, enables);
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pci_read_config_byte(dev1, 0x9, &enables);
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printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
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/* standard bios sets master bit. */
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 0x%x\n", enables);
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enables |= 5;
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/* No need for stepping - kevinh@ispiri.com */
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enables &= ~0x80;
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pci_write_config_byte(dev1, 0x4, enables);
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pci_read_config_byte(dev1, 0x4, &enables);
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printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
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#if (!ENABLE_IDE_NATIVE_MODE)
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/* Use compatability mode - per award bios */
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pci_write_config_dword(dev1, 0x10, 0x0);
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pci_write_config_dword(dev1, 0x14, 0x0);
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pci_write_config_dword(dev1, 0x18, 0x0);
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pci_write_config_dword(dev1, 0x1c, 0x0);
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/* Force interrupts to use compat mode - just like Award bios */
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/* !!! FIX moved it to ide_config.inc */
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#endif
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ethernet_fixup();
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usb_on();
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/* Start the rtc */
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rtc_init(0);
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}
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#endif
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