E7505

src/northbridge/intel/E7505/Config

@@ -0,0 +1,10 @@
+#mainboardinit cpu/i786/enable_sse.inc
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit ram/spotcheck.inc
+mainboardinit northbridge/intel/E7501/raminit.inc
+mainboardinit northbridge/intel/E7501/sdram_enable.inc
+mainboardinit sdram/generic_sdram.inc
+#mainboardinit cpu/i786/disable_sse.inc
+mainboardinit sdram/generic_cache_linuxbios.inc
+
+object northbridge.o

src/northbridge/intel/E7505/northbridge.c

@@ -0,0 +1,103 @@
+#include <mem.h>
+#include <pci.h>
+#include <arch/io.h>
+#include <part/sizeram.h>
+#include <printk.h>
+#include <pc80/mc146818rtc.h>
+
+struct mem_range *sizeram(void)
+{
+	static struct mem_range mem[4];
+	/* the units of tolm are 64 KB */
+	/* the units of drb16 are 64 MB */
+	uint16_t tolm, remapbase, remaplimit, drb16;
+	uint16_t tolm_r, remapbase_r, remaplimit_r;
+	uint8_t  drb;
+	int remap_high;
+	
+	/* Calculate and report the top of low memory and 
+	 * any remapping.
+	 */
+	/* Test if the remap memory high option is set */
+        remap_high = 0;
+        if(get_option(&remap_high, "remap_memory_high")){
+                remap_high = 0;
+        }
+	printk_debug("remap_high is %d\n", remap_high);
+	/* get out the value of the highest DRB. This tells the end of 
+	 * physical memory. The units are ticks of 64 MB i.e. 1 means
+	 * 64 MB. 
+	 */
+	pcibios_read_config_byte(0, 0, 0x67, &drb);
+	drb16 = (uint16_t)drb;
+	if(remap_high && (drb16 > 0x08)) {
+		/* We only come here if we have at least 512MB of memory,
+		 * so it is safe to hard code tolm.
+		 * 0x2000 means 512MB 
+		 */
+
+		tolm = 0x2000;
+		/* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
+		if(drb16 > 0x0040) {
+			/* There is more than 4GB of memory put
+			 * the remap window at the end of ram.
+			 */
+			remapbase = drb16;
+			remaplimit = remapbase + 0x38;
+		}
+		else {
+			remapbase = 0x0040;
+			remaplimit = remapbase + (drb16-8);
+		}
+	}
+	else {
+		tolm = (uint16_t)((pci_memory_base >> 16)&0x0f800);
+		if((tolm>>8) >= (drb16<<2)) {
+			tolm = (drb16<<10);
+			remapbase = 0x3ff;
+			remaplimit = 0;
+		}
+		else {
+			remapbase = drb16;
+			remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
+		}
+	}
+	/* Write the ram configruation registers,
+	 * preserving the reserved bits.
+	 */
+	pcibios_read_config_word(0, 0, 0xc4, &tolm_r);
+	tolm |= (tolm_r & 0x7ff); 
+	pcibios_write_config_word(0, 0, 0xc4, tolm);
+	pcibios_read_config_word(0, 0, 0xc6, &remapbase_r);
+	remapbase |= (remapbase_r & 0xfc00);
+	pcibios_write_config_word(0, 0, 0xc6, remapbase);
+	pcibios_read_config_word(0, 0, 0xc8, &remaplimit_r);
+	remaplimit |= (remaplimit_r & 0xfc00);
+	pcibios_write_config_word(0, 0, 0xc8, remaplimit);
+
+#if 0
+    printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
+#endif
+	
+	mem[0].basek = 0;
+	mem[0].sizek = 640;
+	mem[1].basek = 768;
+	/* Convert size in 64K bytes to size in K bytes */
+	mem[1].sizek = (tolm << 6) - mem[1].basek;
+	mem[2].basek = 0;
+	mem[2].sizek = 0;
+	if ((drb << 16) > (tolm << 6)) {
+		/* We don't need to consider the remap window
+		 * here because we put it immediately after the
+		 * rest of ram.
+		 * All we must do is calculate the amount
+		 * of unused memory and report it at 4GB.
+		 */
+		mem[2].basek = 4096*1024;
+		mem[2].sizek = (drb << 16) - (tolm << 6);
+	}
+	mem[3].basek = 0;
+	mem[3].sizek = 0;
+	
+	return mem;
+}

src/northbridge/intel/E7505/reset_test.inc

@@ -0,0 +1,10 @@
+#define MCH_DRC 0x7c
+#define DRC_DONE (1 << 29)
+	/* If I have already booted once skip a bunch of initialization */
+	/* To see if I have already booted I check to see if memory
+	 * has been enabled.
+	 */
+	movl	$MCH_DRC, %eax
+	PCI_READ_CONFIG_DWORD
+	testl	$DRC_DONE, %eax
+	setnz	%al

src/northbridge/intel/E7505/sdram_enable.inc

@@ -0,0 +1,132 @@
+jmp sdram_enable_out
+
+#ifndef RAM_NOP
+#error RAM_NOP not defined
+#endif
+
+#ifndef RAM_PRECHARGE
+#error RAM_PRECHARGE not defined
+#endif
+
+#ifndef RAM_EMRS
+#error RAM_EMRS not defined
+#endif
+
+#ifndef RAM_MRS
+#error RAM_MRS not defined
+#endif
+
+#ifndef RAM_CBR
+#error RAM_CBR not defined
+#endif
+
+#ifndef RAM_NORMAL
+#error RAM_NORMAL not defined
+#endif
+
+#if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
+ram_enable_1:	.string "Ram Enable 1\r\n"
+ram_enable_2:	.string "Ram Enable 2\r\n"
+ram_enable_3:	.string "Ram Enable 3\r\n"
+ram_enable_4:	.string "Ram Enable 4\r\n"
+ram_enable_5:	.string "Ram Enable 5\r\n"
+ram_enable_6:	.string "Ram Enable 6\r\n"
+ram_enable_7:	.string "Ram Enable 7\r\n"
+ram_enable_8:	.string "Ram Enable 8\r\n"
+ram_enable_9:	.string "Ram Enable 9\r\n"
+ram_enable_10:	.string "Ram Enable 10\r\n"
+ram_enable_11:	.string "Ram Enable 11\r\n"
+#endif
+
+	/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
+	/* delay for 200us */
+
+#define DO_DELAY \
+	movl $16, %edi		; \
+1:	SLOW_DOWN_IO		; \
+	decl %edi		; \
+	jnz 1b
+		
+
+#define EXTRA_DELAY DO_DELAY
+
+enable_sdram:
+	/* 1 & 2 Power up and start clocks */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_1)
+	CONSOLE_DEBUG_TX_STRING($ram_enable_2)
+
+	/* A 200us delay is needed */
+
+	DO_DELAY
+	EXTRA_DELAY
+
+	/* 3. Apply NOP */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_3)
+	RAM_NOP()
+	EXTRA_DELAY
+
+	/* 4 Precharge all */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_4)
+	RAM_PRECHARGE()
+	EXTRA_DELAY
+	
+	/* wait until the all banks idle state... */
+	/* 5. Issue EMRS to enable DLL */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_5)
+	RAM_EMRS()
+	EXTRA_DELAY
+	
+	/* 6. Reset DLL */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_6)
+	RAM_MRS(1)
+	EXTRA_DELAY
+
+	/* Ensure a 200us delay between the DLL reset in step 6 and the final
+	 * mode register set in step 9.
+	 * Infineon needs this before any other command is sent to the ram.
+	 */
+	DO_DELAY
+	EXTRA_DELAY
+	
+	/* 7 Precharge all */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_7)
+	RAM_PRECHARGE()
+	EXTRA_DELAY
+	
+	/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_8)
+	RAM_CBR()
+	EXTRA_DELAY
+	RAM_CBR()
+	EXTRA_DELAY
+	/* And for good luck 6 more CBRs */
+	RAM_CBR()
+	EXTRA_DELAY
+	RAM_CBR()
+	EXTRA_DELAY
+	RAM_CBR()
+	EXTRA_DELAY
+	RAM_CBR()
+	EXTRA_DELAY
+	RAM_CBR()
+	EXTRA_DELAY
+	RAM_CBR()
+	EXTRA_DELAY
+
+	/* 9 mode register set */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_9)
+	RAM_MRS(0)
+	EXTRA_DELAY
+	
+	/* 10 DDR Receive FIFO RE-Sync */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_10)
+	RAM_RESET_DDR_PTR()
+	EXTRA_DELAY
+	
+	/* 11 normal operation */
+	CONSOLE_DEBUG_TX_STRING($ram_enable_11)
+	RAM_NORMAL()
+
+	RET_LABEL(enable_sdram)
+
+sdram_enable_out: