baytrail/rambi: S3 support and other updates

baytrail: Change all GPIO related pull resistors from 10K to 20K
Reviewed-on: https://chromium-review.googlesource.com/187570
(cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)

baytrail: workaround kernel using serial console on resume
Reviewed-on: https://chromium-review.googlesource.com/188011
(cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)

baytrail: allow dirty cache line evictions for SMRAM to stick
Reviewed-on: https://chromium-review.googlesource.com/188015
(cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)

baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
Reviewed-on: https://chromium-review.googlesource.com/188260
(cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)

rambi: always load option rom
Reviewed-on: https://chromium-review.googlesource.com/188721
(cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)

baytrail: use new chromeos ram oops API
Reviewed-on: https://chromium-review.googlesource.com/186394
(cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)

rambi: always show dev/rec screens on eDP connected panel
Reviewed-on: https://chromium-review.googlesource.com/188731
(cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)

baytrail: stop e820 reserving default SMM region
Reviewed-on: https://chromium-review.googlesource.com/189084
(cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)

baytrai: update MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/189196
(cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)

rambi: Put LPE device into ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/189371
(cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)

baytrail: DPTF: Enable mainboard-specific PPCC
Reviewed-on: https://chromium-review.googlesource.com/189576
(cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)

baytrail: Add config option for PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189994
(cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)

rambi: Enable PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189995
(cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)

Squashed 13 commits for baytrail/rambi.

Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6957
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

src/mainboard/google/rambi/Kconfig

@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_RESUME
 	select MAINBOARD_HAS_CHROMEOS
+	select ALWAYS_LOAD_OPROM
 
 config VBOOT_RAMSTAGE_INDEX
 	hex

src/mainboard/google/rambi/acpi/dptf.asl

@@ -49,5 +49,26 @@ Name (DTRT, Package () {
 	Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
 })
 
+Name (MPPC, Package ()
+{
+	0x2,		// Revision
+	Package () {	// Power Limit 1
+		0,	// PowerLimitIndex, 0 for Power Limit 1
+		1600,	// PowerLimitMinimum
+		6200,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		200	// StepSize
+	},
+	Package () {	// Power Limit 2
+		1,	// PowerLimitIndex, 1 for Power Limit 2
+		8000,	// PowerLimitMinimum
+		8000,	// PowerLimitMaximum
+		1000,	// TimeWindowMinimum
+		1000,	// TimeWindowMaximum
+		1000	// StepSize
+	}
+})
+
 /* Include Baytrail DPTF */
 #include <soc/intel/baytrail/acpi/dptf/dptf.asl>

src/mainboard/google/rambi/devicetree.cb

@@ -32,8 +32,12 @@ chip soc/intel/baytrail
 	register "sdcard_cap_high" = "0x0"
 
 	# Enable devices in ACPI mode
-	register "scc_acpi_mode" = "1"
+	register "lpe_acpi_mode" = "1"
 	register "lpss_acpi_mode" = "1"
+	register "scc_acpi_mode" = "1"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
 
 	# Enable PIPEA as DP_C
 	register "gpu_pipea_hotplug" = "6"		# 6ms Pulse

src/mainboard/google/rambi/mainboard.c

@@ -67,15 +67,15 @@ static int int15_handler(void)
 		 * Boot Display Device Hook:
 		 *  bit 0 = CRT
 		 *  bit 1 = TV (eDP) *
-		 *  bit 2 = EFP *
+		 *  bit 2 = EFP
 		 *  bit 3 = LFP
 		 *  bit 4 = CRT2
-		 *  bit 5 = TV2 (eDP) *
+		 *  bit 5 = TV2 (eDP)
-		 *  bit 6 = EFP2 *
+		 *  bit 6 = EFP2
 		 *  bit 7 = LFP2
 		 */
 		X86_AX = 0x005f;
-		X86_CX = 0x0006;
+		X86_CX = 0x0002;
 		res = 1;
 		break;
 	case 0x5f51:

src/soc/intel/baytrail/Kconfig

@@ -10,6 +10,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
+	select BACKUP_DEFAULT_SMM_REGION
 	select CACHE_MRC_SETTINGS
 	select CAR_MIGRATION
 	select COLLECT_TIMESTAMPS

src/soc/intel/baytrail/acpi/dptf/cpu.asl

@@ -127,26 +127,11 @@ Device (TCPU)
 		}
 	}
 
-	Name (PPCC, Package ()
+	/* Return PPCC table defined by mainboard */
+	Method (PPCC)
 	{
-		0x2,		// Revision
+		Return (\_SB.MPPC)
-		Package () {	// Power Limit 1
+	}
-			0,	// PowerLimitIndex, 0 for Power Limit 1
-			1600,	// PowerLimitMinimum
-			6200,	// PowerLimitMaximum
-			1000,	// TimeWindowMinimum
-			1000,	// TimeWindowMaximum
-			200	// StepSize
-		},
-		Package () {	// Power Limit 2
-			1,	// PowerLimitIndex, 1 for Power Limit 2
-			8000,	// PowerLimitMinimum
-			8000,	// PowerLimitMaximum
-			1000,	// TimeWindowMinimum
-			1000,	// TimeWindowMaximum
-			1000	// StepSize
-		}
-	})
 
 #ifdef DPTF_CPU_CRITICAL
 	Method (_CRT)

src/soc/intel/baytrail/acpi/southcluster.asl

@@ -198,10 +198,6 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
 		Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
 		Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
-#if CONFIG_CHROMEOS_RAMOOPS
-		Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
-					 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
-#endif
 	})
 
 	// Current Resource Settings

src/soc/intel/baytrail/baytrail/gpio.h

@@ -163,6 +163,13 @@
 	  .use_sel   = GPIO_USE_MMIO, \
 	  .is_gpio   = 1 }
 
+#define GPIO_INPUT_PU_20K \
+	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \
+	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+	  .pad_val   = PAD_VAL_INPUT, \
+	  .use_sel   = GPIO_USE_MMIO, \
+	  .is_gpio   = 1 }
+
 #define GPIO_INPUT_PD_10K \
 	{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
@@ -170,15 +177,22 @@
 	  .use_sel   = GPIO_USE_MMIO, \
 	  .is_gpio   = 1 }
 
+#define GPIO_INPUT_PD_20K \
+	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
+	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+	  .pad_val   = PAD_VAL_INPUT, \
+	  .use_sel   = GPIO_USE_MMIO, \
+	  .is_gpio   = 1 }
+
 #define GPIO_INPUT_NOPU \
-	{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
+	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, \
 	  .use_sel   = GPIO_USE_MMIO, \
 	  .is_gpio   = 1 }
 
 #define GPIO_INPUT_LEGACY_NOPU \
-	{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
+	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, \
 	  .use_sel   = GPIO_USE_LEGACY, \
@@ -187,7 +201,7 @@
 
 /* Direct / dedicated IRQ input - pass signal directly to apic */
 #define GPIO_DIRQ \
-	{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
+	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
@@ -220,13 +234,13 @@
 	  .pad_val   = PAD_VAL_DEFAULT }
 
 /* Default functional configs -- no PU */
-#define GPIO_FUNC0		GPIO_FUNC(0, PULL_DISABLE, 10K)
+#define GPIO_FUNC0		GPIO_FUNC(0, PULL_DISABLE, 20K)
-#define GPIO_FUNC1		GPIO_FUNC(1, PULL_DISABLE, 10K)
+#define GPIO_FUNC1		GPIO_FUNC(1, PULL_DISABLE, 20K)
-#define GPIO_FUNC2		GPIO_FUNC(2, PULL_DISABLE, 10K)
+#define GPIO_FUNC2		GPIO_FUNC(2, PULL_DISABLE, 20K)
-#define GPIO_FUNC3		GPIO_FUNC(3, PULL_DISABLE, 10K)
+#define GPIO_FUNC3		GPIO_FUNC(3, PULL_DISABLE, 20K)
-#define GPIO_FUNC4		GPIO_FUNC(4, PULL_DISABLE, 10K)
+#define GPIO_FUNC4		GPIO_FUNC(4, PULL_DISABLE, 20K)
-#define GPIO_FUNC5		GPIO_FUNC(5, PULL_DISABLE, 10K)
+#define GPIO_FUNC5		GPIO_FUNC(5, PULL_DISABLE, 20K)
-#define GPIO_FUNC6		GPIO_FUNC(6, PULL_DISABLE, 10K)
+#define GPIO_FUNC6		GPIO_FUNC(6, PULL_DISABLE, 20K)
 
 /* ACPI GPIO routing. Assume everything is externally pulled and negative edge
  * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */
@@ -265,9 +279,9 @@
 /* Common default GPIO settings */
 #define GPIO_INPUT 		GPIO_INPUT_NOPU
 #define GPIO_INPUT_LEGACY	GPIO_INPUT_LEGACY_NOPU
-#define GPIO_INPUT_PU		GPIO_INPUT_PU_10K
+#define GPIO_INPUT_PU		GPIO_INPUT_PU_20K
-#define GPIO_INPUT_PD 		GPIO_INPUT_PD_10K
+#define GPIO_INPUT_PD 		GPIO_INPUT_PD_20K
-#define GPIO_NC			GPIO_INPUT_PU_10K
+#define GPIO_NC			GPIO_INPUT_PU_20K
 #define GPIO_DEFAULT 		GPIO_FUNC0
 
 /* 16 DirectIRQs per supported bank */
@@ -320,7 +334,7 @@ struct gpio_bank {
 	const u8 gpio_f1_range_end;
 };
 
-void setup_soc_gpios(struct soc_gpio_config *config);
+void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap);
 /* This function is weak and can be overridden by a mainboard function. */
 struct soc_gpio_config* mainboard_get_gpios(void);
 

src/soc/intel/baytrail/baytrail/iosf.h

@@ -197,10 +197,18 @@ void iosf_ssus_write(int reg, uint32_t val);
 #define BUNIT_BMBOUND_HI	0x26
 #define BUNIT_MMCONF_REG	0x27
 /* The SMMRR registers define the SMM region in MiB granularity. */
+#define BUNIT_SMRCP		0x2b
+#define BUNIT_SMRRAC		0x2c
+#define BUNIT_SMRWAC		0x2d
 #define BUNIT_SMRRL		0x2e
 #define BUNIT_SMRRH		0x2f
 # define BUNIT_SMRR_ENABLE	(1 << 31)
 
+/* SA ID bits. */
+#define SAI_IA_UNTRUSTED	(1 << 0)
+#define SAI_IA_SMM		(1 << 2)
+#define SAI_IA_BOOT		(1 << 4)
+
 /*
  * DUNIT Registers.
  */

src/soc/intel/baytrail/baytrail/mrc_wrapper.h

@@ -28,7 +28,7 @@
 #ifndef _MRC_WRAPPER_H_
 #define _MRC_WRAPPER_H_
 
-#define MRC_PARAMS_VER  4
+#define MRC_PARAMS_VER  5
 
 #define NUM_CHANNELS 2
 
@@ -55,12 +55,25 @@ enum mrc_wrapper_error {
 	PLATFORM_SETTINGS_FAIL = -4,
 	DIMM_DETECTION_FAILURE = -5,
 	MEMORY_CONFIG_FAILURE = -6,
+	INVALID_CPU_ODT_SETTING = -7,
+	INVALID_DRAM_ODT_SETTING = -8,
 };
 
 struct mrc_mainboard_params {
 	int dram_type;
 	int dram_info_location; /* DRAM_INFO_* */
-	int weaker_odt_settings; /* Apply weaker on-die-termination settings. */
+	int dram_is_slotted; /* mobo has DRAM slots. */
+	/*
+	 * The below ODT settings are only honored when !dram_is_slotted.
+	 * Aditionally, weaker_odt_settings being non-zero causes
+	 * cpu_odt_value to not be honored as weaker_odt_settings have a
+	 * special training path.
+	 */
+	int weaker_odt_settings;
+	/* Allowed settings: 60, 80, 100, 120, and 150. */
+	int cpu_odt_value;
+	/* Allowed settings: 60 and 120. */
+	int dram_odt_value;
 	int spd_addrs[NUM_CHANNELS];
 	void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */
 } __attribute__((packed));

src/soc/intel/baytrail/baytrail/ramstage.h

@@ -21,10 +21,11 @@
 #define _BAYTRAIL_RAMSTAGE_H_
 
 #include <device/device.h>
+#include <chip.h>
 
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */
-void baytrail_init_pre_device(void);
+void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
 void baytrail_init_cpus(device_t dev);
 void set_max_freq(void);
 void southcluster_enable_dev(device_t dev);

src/soc/intel/baytrail/baytrail/smm.h

@@ -37,7 +37,13 @@ void *smm_region_start(void);
 #include <stdint.h>
 void southcluster_smm_clear_state(void);
 void southcluster_smm_enable_smi(void);
-void southcluster_smm_save_gpio_route(uint32_t route);
+void southcluster_smm_save_param(int param, uint32_t data);
 #endif
 
+enum {
+	SMM_SAVE_PARAM_GPIO_ROUTE = 0,
+	SMM_SAVE_PARAM_PCIE_WAKE_ENABLE,
+	SMM_SAVE_PARAM_COUNT
+};
+
 #endif /* _BAYTRAIL_SMM_H_ */

src/soc/intel/baytrail/chip.c

@@ -70,7 +70,7 @@ static void enable_dev(device_t dev)
 /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
 static void soc_init(void *chip_info)
 {
-	baytrail_init_pre_device();
+	baytrail_init_pre_device(chip_info);
 }
 
 struct chip_operations soc_intel_baytrail_ops = {

src/soc/intel/baytrail/chip.h

@@ -26,9 +26,10 @@
 #include <stdint.h>
 
 struct soc_intel_baytrail_config {
-        uint8_t sata_port_map;
+	uint8_t enable_xdp_tap;
-        uint8_t sata_ahci;
+	uint8_t sata_port_map;
-        uint8_t ide_legacy_combined;
+	uint8_t sata_ahci;
+	uint8_t ide_legacy_combined;
 	uint8_t clkreq_enable;
 
 	/* VR low power settings -- enable PS2 mode for gfx and core */
@@ -68,6 +69,9 @@ struct soc_intel_baytrail_config {
 	int scc_acpi_mode;
 	int lpe_acpi_mode;
 
+	/* Allow PCIe devices to wake system from suspend. */
+	int pcie_wake_enable;
+
 	/*
 	 * Digital Port Hotplug Enable:
 	 *  0x04 = Enabled, 2ms short pulse

src/soc/intel/baytrail/cpu.c

@@ -30,6 +30,7 @@
 #include <cpu/x86/smm.h>
 #include <reg_script.h>
 
+#include <baytrail/iosf.h>
 #include <baytrail/msr.h>
 #include <baytrail/pattrs.h>
 #include <baytrail/ramstage.h>
@@ -103,6 +104,8 @@ void baytrail_init_cpus(device_t dev)
 	struct bus *cpu_bus = dev->link_list;
 	const struct pattrs *pattrs = pattrs_get();
 	struct mp_params mp_params;
+	uint32_t bsmrwac;
+	void *default_smm_area;
 
 	/* Set up MTRRs based on physical address size. */
 	x86_setup_fixed_mtrrs();
@@ -116,6 +119,16 @@ void baytrail_init_cpus(device_t dev)
 	mp_params.num_records = ARRAY_SIZE(mp_steps);
 	mp_params.microcode_pointer = pattrs->microcode_patch;
 
+	default_smm_area = backup_default_smm_area();
+
+	/*
+	 * Configure the BUNIT to allow dirty cache line evictions in non-SMM
+	 * mode for the lines that were dirtied while in SMM mode. Otherwise
+	 * the writes would be silently dropped.
+	 */
+	bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
+	iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
+
 	/* Set package MSRs */
 	reg_script_run(package_msr_script);
 
@@ -125,6 +138,8 @@ void baytrail_init_cpus(device_t dev)
 	if (mp_init(cpu_bus, &mp_params)) {
 		printk(BIOS_ERR, "MP initialization failure.\n");
 	}
+
+	restore_default_smm_area(default_smm_area);
 }
 
 static void baytrail_core_init(device_t cpu)

src/soc/intel/baytrail/gpio.c

@@ -192,7 +192,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 			route_reg |= ROUTE_SCI << (2 * (i + 8));
 		}
 	}
-	southcluster_smm_save_gpio_route(route_reg);
+	southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
 static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
@@ -214,7 +214,7 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
 	}
 }
 
-void setup_soc_gpios(struct soc_gpio_config *config)
+void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 {
 	if (config) {
 		setup_gpios(config->ncore, &gpncore_bank);
@@ -228,6 +228,14 @@ void setup_soc_gpios(struct soc_gpio_config *config)
 			setup_dirqs(*config->sus_dirq, &gpssus_bank);
 	}
 
+	/* Set on die termination feature with pull up value and
+	 * drive the pad high for TAP_TDO and TAP_TMS
+	 */
+	if (!enable_xdp_tap) {
+		printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
+		write32(GPSSUS_PAD_BASE + 0x2fc, 0xc);
+		write32(GPSSUS_PAD_BASE + 0x2cc, 0xc);
+	}
 }
 
 struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)

src/soc/intel/baytrail/northcluster.c

@@ -22,6 +22,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #include <baytrail/iomap.h>
 #include <baytrail/iosf.h>
@@ -88,14 +89,8 @@ static void nc_read_resources(device_t dev)
 	mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
 	mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
 
-	/* 0 -> SMM_DEFAULT_BASE cacheable ram. */
+	/* 0 -> 0xa0000 */
-	ram_resource(dev, index++, 0, RES_IN_KiB(SMM_DEFAULT_BASE));
+	base_k = RES_IN_KiB(0);
-	/* Default SMM region is cacheable but reserved for coreboot */
-	reserved_ram_resource(dev, index++, RES_IN_KiB(SMM_DEFAULT_BASE),
-	                      RES_IN_KiB(SMM_DEFAULT_SIZE));
-
-	/* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE - > 0xa0000 */
-	base_k = RES_IN_KiB(SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE);
 	size_k = RES_IN_KiB(0xa0000) - base_k;
 	ram_resource(dev, index++, base_k, size_k);
 
@@ -132,11 +127,8 @@ static void nc_read_resources(device_t dev)
 	mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
 	reserved_ram_resource(dev, index++, (0xc0000 >> 10),
 	                      (0x100000 - 0xc0000) >> 10);
-#if CONFIG_CHROMEOS_RAMOOPS
+
-	reserved_ram_resource(dev, index++,
+	chromeos_reserve_ram_oops(dev, index++);
-			CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
-			CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
-#endif
 }
 
 static struct device_operations nc_ops = {

src/soc/intel/baytrail/pcie.c

@@ -27,6 +27,7 @@
 #include <baytrail/pci_devs.h>
 #include <baytrail/pcie.h>
 #include <baytrail/ramstage.h>
+#include <baytrail/smm.h>
 
 #include "chip.h"
 
@@ -174,10 +175,15 @@ static void check_device_present(device_t dev)
 static void byt_pcie_enable(device_t dev)
 {
 	if (is_first_port(dev)) {
+		struct soc_intel_baytrail_config *config = dev->chip_info;
 		uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
 		pll_en_off = !!(reg & PLL_OFF_EN);
 
 		strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
+
+		if (config && config->pcie_wake_enable)
+			southcluster_smm_save_param(
+				SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
 	}
 
 	/* Check if device is enabled in strapping. */

src/soc/intel/baytrail/ramstage.c

@@ -184,9 +184,9 @@ static void s3_resume_prepare(void)
 	s3_save_acpi_wake_source(gnvs);
 }
 
-void baytrail_init_pre_device(void)
+void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
 {
-	struct soc_gpio_config *config;
+	struct soc_gpio_config *gpio_config;
 
 	fill_in_pattrs();
 
@@ -200,8 +200,8 @@ void baytrail_init_pre_device(void)
 	baytrail_run_reference_code();
 
 	/* Get GPIO initial states from mainboard */
-	config = mainboard_get_gpios();
+	gpio_config = mainboard_get_gpios();
-	setup_soc_gpios(config);
+	setup_soc_gpios(gpio_config, config->enable_xdp_tap);
 
 	baytrail_init_scc();
 }

src/soc/intel/baytrail/smm.c

@@ -31,13 +31,12 @@
 #include <baytrail/pmc.h>
 #include <baytrail/smm.h>
 
-/* Save the gpio route register. The settings are committed from
+/* Save settings which will be committed in SMI functions. */
- * southcluster_smm_enable_smi(). */
+static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
-static uint32_t gpio_route;
 
-void southcluster_smm_save_gpio_route(uint32_t route)
+void southcluster_smm_save_param(int param, uint32_t data)
 {
-	gpio_route = route;
+	smm_save_params[param] = data;
 }
 
 void southcluster_smm_clear_state(void)
@@ -70,7 +69,7 @@ static void southcluster_smm_route_gpios(void)
 	const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
 	uint32_t alt_gpio_reg = 0;
-	uint32_t route_reg = gpio_route;
+	uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];
 	int i;
 
 	printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
@@ -92,10 +91,12 @@ static void southcluster_smm_route_gpios(void)
 
 void southcluster_smm_enable_smi(void)
 {
+	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
-	/* Configure events Disable pcie wake. */
+	if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
-	enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+		pm1_events |= PCIEXPWAK_DIS;
+	enable_pm1(pm1_events);
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */

src/soc/intel/baytrail/southcluster.c

@@ -20,6 +20,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <arch/acpi.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -29,6 +30,7 @@
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
+#include <drivers/uart/uart8250reg.h>
 
 #include <baytrail/iomap.h>
 #include <baytrail/irq.h>
@@ -144,6 +146,42 @@ static void sc_rtc_init(void)
 	rtc_init(rtc_fail);
 }
 
+/*
+ * The UART hardware loses power while in suspend. Because of this the kernel
+ * can hang because it doesn't re-initialize serial ports it is using for
+ * consoles at resume time. The following function configures the UART
+ * if the hardware is enabled though it may not be the correct baud rate
+ * or configuration.  This is definitely a hack, but it helps the kernel
+ * along.
+ */
+static void com1_configure_resume(device_t dev)
+{
+	const uint16_t port = 0x3f8;
+
+	/* Is the UART I/O port eanbled? */
+	if (!(pci_read_config32(dev, UART_CONT) & 1))
+		return;
+
+	/* Disable interrupts */
+	outb(0x0, port + UART8250_IER);
+
+	/* Enable FIFOs */
+	outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR);
+
+	/* assert DTR and RTS so the other end is happy */
+	outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR);
+
+	/* DLAB on */
+	outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR);
+
+	/* Set Baud Rate Divisor. 1 ==> 115200 Baud */
+	outb(1, port + UART8250_DLL);
+	outb(0, port + UART8250_DLM);
+
+	/* Set to 3 for 8N1 */
+	outb(3, port + UART8250_LCR);
+}
+
 static void sc_init(device_t dev)
 {
 	int i;
@@ -176,6 +214,9 @@ static void sc_init(device_t dev)
 		write32(gen_pmcon1,
 			read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
 	}
+
+	if (acpi_slp_type == 3)
+		com1_configure_resume(dev);
 }
 
 /*