From 31edcc58dc2fc5e77603acb960ce2416b61f9203 Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Wed, 10 Dec 2008 18:50:54 +0000 Subject: [PATCH] This patch removes some warnings from the v3 kontron build. Two unused variables, an incorrect pointer type, and two printf format warnings. Signed-off-by: Myles Watson Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://coreboot.org/repository/coreboot-v3@1068 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- mainboard/kontron/986lcd-m/stage1.c | 4 +++- northbridge/intel/i945/northbridge.c | 12 ++++++------ northbridge/intel/i945/raminit.c | 4 ++-- southbridge/intel/i82801gx/pci.c | 2 +- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/mainboard/kontron/986lcd-m/stage1.c b/mainboard/kontron/986lcd-m/stage1.c index bf6c7e3211..781115435a 100644 --- a/mainboard/kontron/986lcd-m/stage1.c +++ b/mainboard/kontron/986lcd-m/stage1.c @@ -207,7 +207,9 @@ void hardware_stage1(void) { void early_superio_config_w83627thg(void); void ich7_enable_lpc(void); - int boot_mode = 0; + +#warning Reboot won't work until this is fixed. + #if 1 /* hack */ pci_conf1_write_config32(PCI_BDF(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); diff --git a/northbridge/intel/i945/northbridge.c b/northbridge/intel/i945/northbridge.c index 9d0e60afc5..2cc38f1b3a 100644 --- a/northbridge/intel/i945/northbridge.c +++ b/northbridge/intel/i945/northbridge.c @@ -179,17 +179,17 @@ static unsigned int i945_pci_domain_scan_bus(struct device * dev, unsigned int m #warning get number of 945 pci domain ops struct device_operations i945_pci_domain_ops = { .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_INTEL, - .device = 0x6789}}}, + {.pci = {.vendor = PCI_VENDOR_ID_INTEL, + .device = 0x6789}}}, .constructor = default_device_constructor, - .reset_bus = pci_bus_reset, + .reset_bus = pci_bus_reset, .phase3_scan = i945_pci_domain_scan_bus, .phase4_read_resources = I945_pci_domain_read_resources, .phase4_set_resources = I945_pci_domain_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = NULL, .ops_pci = &pci_dev_ops_pci, - .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ + .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ }; static void mc_read_resources(struct device * dev) @@ -212,8 +212,8 @@ static void mc_read_resources(struct device * dev) IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (u64) resource->base, (u64) (resource->base + resource->size)); + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08llx-0x%08llx.\n", + resource->base, resource->base + resource->size); } static void mc_set_resources(struct device * dev) diff --git a/northbridge/intel/i945/raminit.c b/northbridge/intel/i945/raminit.c index 5bbd5cb9d5..68811cb81c 100644 --- a/northbridge/intel/i945/raminit.c +++ b/northbridge/intel/i945/raminit.c @@ -1069,8 +1069,8 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; - const u8 * strength_multiplier; - const u8* const * slew_group_lookup; + const u8 *strength_multiplier; + const u8 *slew_group_lookup; int idx; /* Set Strength Multipliers */ diff --git a/southbridge/intel/i82801gx/pci.c b/southbridge/intel/i82801gx/pci.c index d1dc232e16..4b6745aa7e 100644 --- a/southbridge/intel/i82801gx/pci.c +++ b/southbridge/intel/i82801gx/pci.c @@ -57,7 +57,6 @@ static void pci_init(struct device *dev) static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; - u16 command; /* Set the subsystem vendor and device id for mainboard devices */ ops = ops_pci(dev); @@ -72,6 +71,7 @@ static void ich_pci_dev_enable_resources(struct device *dev) } #if 0 + u16 command; /* If we write to PCI_COMMAND, on some systems * this will cause the ROM and APICs not being visible * anymore.