mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
We're getting closer. It has been pointed out that this code is not pretty. I agree. Get
it working, then we'll get it pretty. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
c945259136
commit
30c0db46ed
10 changed files with 192 additions and 79 deletions
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@ -42,6 +42,13 @@ $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c: $(obj)/util/options/build_opt_t
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--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
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--option $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
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$(obj)/mainboard/$(MAINBOARDDIR)/option_table.h: $(obj)/util/options/build_opt_tbl $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout
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$(Q)printf " OPTIONS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
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$(Q)$(obj)/util/options/build_opt_tbl -b \
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--config $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout \
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--header $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
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$(obj)/option_table: $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o
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$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(OBJCOPY) -O binary $< $@
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@ -22,6 +22,7 @@
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#include <lib.h>
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#include <console.h>
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#include <msr.h>
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#include <macros.h>
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#include <amd/k8/k8.h>
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/**
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@ -17,11 +17,11 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "../macros.h"
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#define ASSEMBLY
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#include <macros.h>
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#define CacheSize CONFIG_CARSIZE
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#define CacheBase CONFIG_CARBASE
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#define MEM_TOPK 2048
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#define ASSEMBLY
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/* leave some space for global variable to pass to RAM stage */
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#define GlobalVarSize 32
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@ -1,29 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000 Ron G. Minnich <rminnich@lanl.gov>
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* Copyright (C) 2007 Stefan Reinauer <stepan@coresystems.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef ARCH_X86_MACROS_H
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#define ARCH_X86_MACROS_H
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#define port80_post(value) \
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movb $value, %al; \
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outb %al, $0x80
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#endif /* ARCH_X86_MACROS_H */
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@ -322,4 +322,14 @@ int check_normal_boot_flag(void)
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return (byte & RTC_NORMAL_BOOT_FLAG_SET);
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}
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unsigned read_option(unsigned start, unsigned size, unsigned def)
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{
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#ifdef CONFIG_OPTION_TABLE
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unsigned byte;
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byte = CMOS_READ(start/8);
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return (byte >> (start & 7U)) & ((1U << size) - 1U);
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#else
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return def;
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#endif
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}
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2006-2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -282,3 +282,124 @@
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#define NBCAP_MEMCLK_166MHZ 1
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#define NBCAP_MEMCLK_200MHZ 0
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#define NBCAP_MEMCTRL (1 << 8)
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/* resources for the routing in the northbridge. These may be family specific;
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* the were in v2.
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*/
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#define RES_DEBUG 0
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#define RES_PCI_IO 0x10
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#define RES_PORT_IO_8 0x22
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#define RES_PORT_IO_32 0x20
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#define RES_MEM_IO 0x40
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#ifndef ASSEMBLY
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/* cpu version -- no support for f0 yet */
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static inline int is_cpu_rev_a0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f00;
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}
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static inline int is_cpu_pre_c0(void)
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{
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return (cpuid_eax(1) & 0xfffef) < 0x0f48;
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}
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static inline int is_cpu_c0(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f48;
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}
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static inline int is_cpu_pre_b3(void)
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{
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return (cpuid_eax(1) & 0xfffef) < 0x0f41;
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}
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static inline int is_cpu_b3(void)
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{
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return (cpuid_eax(1) & 0xfffef) == 0x0f41;
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}
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//AMD_D0_SUPPORT
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static inline int is_cpu_pre_d0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x10f00;
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}
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static inline int is_cpu_d0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) == 0x10f00;
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}
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//AMD_E0_SUPPORT
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static inline int is_cpu_pre_e0(void)
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{
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return (cpuid_eax(1) & 0xfff0f) < 0x20f00;
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}
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static inline int is_cpu_e0(void)
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{
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return (cpuid_eax(1) & 0xfff00) == 0x20f00;
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}
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/* note: we'd like to have this sysinfo common to all K8, there's no need to
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* have one different kind per different kind of k8 at this point.
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*/
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//#include "raminit.h"
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struct dimm_size {
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u8 per_rank; // it is rows + col + bank_lines + data lines */
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u8 rows;
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u8 col;
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u8 bank; //1, 2, 3 mean 2, 4, 8
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u8 rank;
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} __attribute__((packed));
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struct mem_info { // pernode
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u32 dimm_mask;
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struct dimm_size sz[DIMM_SOCKETS];
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u32 x4_mask;
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u32 x16_mask;
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u32 single_rank_mask;
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u32 page_1k_mask;
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// u32 ecc_mask;
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// u32 registered_mask;
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u8 is_opteron;
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u8 is_registered;
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u8 is_ecc;
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u8 is_Width128;
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u8 memclk_set; // we need to use this to retrieve the mem param
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u8 rsv[3];
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} __attribute__((packed));
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struct link_pair_st {
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struct device * udev;
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u32 upos;
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u32 uoffs;
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struct device * dev;
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u32 pos;
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u32 offs;
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} __attribute__((packed));
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struct sys_info {
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u8 ctrl_present[NODE_NUMS];
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struct mem_info meminfo[NODE_NUMS];
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struct mem_controller ctrl[NODE_NUMS];
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u8 mem_trained[NODE_NUMS]; //0: no dimm, 1: trained, 0x80: not started, 0x81: recv1 fail, 0x82: Pos Fail, 0x83:recv2 fail
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u32 tom_k;
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u32 tom2_k;
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u32 mem_base[NODE_NUMS];
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u32 cs_base[NODE_NUMS*8]; //8 cs_idx
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u32 hole_reg[NODE_NUMS]; // can we spare it to one, and put ctrl idx in it
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u8 dqs_delay_a[NODE_NUMS*2*2*9]; //8 node channel 2, direction 2 , bytelane *9
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u8 dqs_rcvr_dly_a[NODE_NUMS*2*8]; //8 node, channel 2, receiver 8
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u32 nodes;
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struct link_pair_st link_pair[16];// enough? only in_conherent
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u32 link_pair_num;
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u32 ht_c_num;
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u32 sbdn;
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u32 sblk;
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u32 sbbusn;
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} __attribute__((packed));
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#endif /* ! ASSEMBLY */
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@ -22,7 +22,7 @@
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#define HC_POSSIBLE_NUM 8
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struct amdk8_sysconf_t {
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struct amdk8_sysconf{
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//ht
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unsigned nodes;
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unsigned hc_possible_num;
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@ -155,33 +155,32 @@
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#define PCI_VENDOR_ID_CIRRUS 0x1013
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#define PCI_DEVICE_ID_CIRRUS_5446 0x00b8 /* Used by QEMU */
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#define PCI_VENDIR_ID_NVIDIA 0x10de
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/*
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0360MCP55 LPC Bridge
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0361MCP55 LPC Bridge
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0362MCP55 LPC Bridge
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0363MCP55 LPC Bridge
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0364MCP55 LPC Bridge
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0365MCP55 LPC Bridge
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0366MCP55 LPC Bridge
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0367MCP55 LPC Bridge
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0368MCP55 SMBus
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0369MCP55 Memory Controller
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036aMCP55 Memory Controller
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036bMCP55 SMU
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036cMCP55 USB Controller
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036dMCP55 USB Controller
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036eMCP55 IDE
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0370MCP55 PCI bridge
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0371MCP55 High Definition Audio
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0372MCP55 Ethernet
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0373MCP55 Ethernet
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0374MCP55 PCI Express bridge
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0375MCP55 PCI Express bridge
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0376MCP55 PCI Express bridge
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0377MCP55 PCI Express bridge
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0378MCP55 PCI Express bridge
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037aMCP55 Memory Controller
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*/
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIBRIDGE 0x370
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#define PCI_VENDOR_ID_NVIDIA 0x10de
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365
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#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368
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#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E
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#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F
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#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372
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#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373
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#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371
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#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C
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#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378
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#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369
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#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A
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#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B
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#endif /* DEVICE_PCI_IDS_H */
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@ -19,7 +19,8 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
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$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
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INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
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@ -32,15 +32,25 @@
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#include <console.h>
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#include <mtrr.h>
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#include <macros.h>
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#include <spd.h>
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#include <cpu.h>
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#include <msr.h>
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#include <amd/k8/raminit.h>
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#include <amd/k8/k8.h>
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#include <amd/k8/sysconf.h>
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#include <device/pci.h>
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#include <mc146818rtc.h>
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#include <lib.h>
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#ifndef QRANK_DIMM_SUPPORT
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#define QRANK_DIMM_SUPPORT 0
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#endif
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#ifndef HW_MEM_HOLE_SIZEK
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#define HW_MEM_HOLE_SIZEK 64*1024*1024
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#endif
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static void hard_reset(void);
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static void setup_resource_map(const unsigned int *register_values, int max)
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@ -566,14 +576,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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static void hw_enable_ecc(const struct mem_controller *ctrl)
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{
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u32 dcl, nbcap;
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u32 dcl, nbcap, opt = 1;
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nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
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dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
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dcl &= ~DCL_DimmEccEn;
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if (nbcap & NBCAP_ECC) {
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dcl |= DCL_DimmEccEn;
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}
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if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
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if (get_option(&opt, "ECC_memory") || opt) {
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dcl &= ~DCL_DimmEccEn;
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}
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pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
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@ -610,16 +620,6 @@ static int is_registered(const struct mem_controller *ctrl)
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return !(dcl & DCL_UnBufDimm);
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}
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struct dimm_size {
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unsigned long side1;
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unsigned long side2;
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unsigned long rows;
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unsigned long col;
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#if QRANK_DIMM_SUPPORT == 1
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unsigned long rank;
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#endif
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};
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static struct dimm_size spd_get_dimm_size(unsigned device)
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{
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/* Calculate the log base 2 size of a DIMM in bits */
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@ -1118,8 +1118,9 @@ unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
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static void order_dimms(const struct mem_controller *ctrl)
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{
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unsigned long tom_k, base_k;
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int opt = 1;
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if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
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if (get_option(&opt, "interleave_chip_selects") || opt) {
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tom_k = interleave_chip_selects(ctrl);
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} else {
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printk(BIOS_DEBUG, "Interleaving disabled\n");
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@ -1405,6 +1406,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
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unsigned min_cycle_time, min_latency, bios_cycle_time;
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int i;
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u32 value;
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u32 max_mem_clk_index = 0;
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static const u8 latency_indicies[] = { 26, 23, 9 };
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static const unsigned char min_cycle_times[] = {
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@ -1417,8 +1419,9 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
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value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
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min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
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bios_cycle_time = min_cycle_times[
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read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
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get_option(&max_mem_clk_index, "max_mem_clk");
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bios_cycle_time = min_cycle_times[max_mem_clk_index];
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if (bios_cycle_time > min_cycle_time) {
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min_cycle_time = bios_cycle_time;
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}
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@ -2111,7 +2114,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sy
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return;
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hw_spd_err:
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/* Unrecoverable error reading SPD data */
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print_err("SPD error - reset\n");
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printk(BIOS_ERR, "SPD error - reset\n");
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hard_reset();
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return;
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}
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Loading…
Add table
Reference in a new issue