mirror of
https://github.com/fail0verflow/switch-coreboot.git
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UPSTREAM: mb/google/oak: replace symbolic links
These three files were added as symbolic links to the other files in the same directory. Delete the links, and copy the real files into their places. Because of the varied environments that coreboot is built in, we don't want to have symbolic links in the tree. These three files were the only cases of symbolic links. BUG=None BRANCH=None TEST=None Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: If69f40c2c4cdcabc4fdfc1d6026a91c0791756da Reviewed-on: https://chromium-review.googlesource.com/415630 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Martin Roth
chrome-bot
parent
05d5d80e38
commit
2fc7b98b69
3 changed files with 348 additions and 3 deletions
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sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc
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{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
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{
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.impedance_drvp = 0x9,
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.impedance_drvn = 0xa,
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.datlat_ucfirst = 19,
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.ca_train = {
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[CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
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[CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
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},
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.ca_train_center = {
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[CHANNEL_A] = 2,
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[CHANNEL_B] = 0
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},
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.wr_level = {
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[CHANNEL_A] = { 5, 6, 5, 6},
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[CHANNEL_B] = { 6, 6, 6, 4}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 28, 64},
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{ 0, 0}
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},
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[CHANNEL_B] = {
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{ 28, 64},
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{ 0, 0}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0x110e0b0b,
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[CHANNEL_B] = 0x12100d0d
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x01040302,
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0x04010300,
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0x02040300,
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0x04030302,
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0x04070400,
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0x07070707,
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0x05070808,
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0x00010404
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},
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[CHANNEL_B] = {
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0x05060604,
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0x04010400,
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0x05070300,
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0x05030504,
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0x07090500,
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0x08090707,
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0x080a0a0a,
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0x02000604
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c0,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0x20102017,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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sdram-lpddr3-H9CCNNN8GTMLAR-2GB.inc
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@ -0,0 +1,116 @@
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{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
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{
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.impedance_drvp = 0x9,
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.impedance_drvn = 0xa,
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.datlat_ucfirst = 19,
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.ca_train = {
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[CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
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[CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
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},
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.ca_train_center = {
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[CHANNEL_A] = 2,
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[CHANNEL_B] = 0
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},
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.wr_level = {
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[CHANNEL_A] = { 5, 6, 5, 6},
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[CHANNEL_B] = { 6, 6, 6, 4}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 28, 64},
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{ 0, 0}
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},
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[CHANNEL_B] = {
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{ 28, 64},
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{ 0, 0}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0x110e0b0b,
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[CHANNEL_B] = 0x12100d0d
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x01040302,
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0x04010300,
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0x02040300,
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0x04030302,
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0x04070400,
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0x07070707,
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0x05070808,
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0x00010404
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},
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[CHANNEL_B] = {
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0x05060604,
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0x04010400,
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0x05070300,
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0x05030504,
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0x07090500,
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0x08090707,
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0x080a0a0a,
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0x02000604
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c0,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0x20102017,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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@ -1 +0,0 @@
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sdram-lpddr3-K4E6E304EB-4GB.inc
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{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */
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{
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.impedance_drvp = 0xc,
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.impedance_drvn = 0xd,
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.datlat_ucfirst = 19,
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.ca_train = {
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[CHANNEL_A] = { 8, 7, 6, 7, 4, 2, 2, 3, 4, 5},
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[CHANNEL_B] = { 0, 0, 1, 0, 0, 5, 5, 3, 6, 5}
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},
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.ca_train_center = {
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[CHANNEL_A] = 2,
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[CHANNEL_B] = 0
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},
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.wr_level = {
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[CHANNEL_A] = { 5, 6, 5, 6},
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[CHANNEL_B] = { 6, 6, 6, 4}
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},
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.gating_win = {
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[CHANNEL_A] = {
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{ 28, 64},
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{ 28, 64}
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},
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[CHANNEL_B] = {
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{ 28, 64},
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{ 28, 64}
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}
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},
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.rx_dqs_dly = {
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[CHANNEL_A] = 0x110e0b0b,
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[CHANNEL_B] = 0x12100d0d
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},
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.rx_dq_dly = {
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[CHANNEL_A] = {
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0x01040302,
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0x04010300,
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0x02040300,
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0x04030302,
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0x04070400,
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0x07070707,
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0x05070808,
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0x00010404
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},
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[CHANNEL_B] = {
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0x05060604,
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0x04010400,
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0x05070300,
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0x05030504,
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0x07090500,
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0x08090707,
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0x080a0a0a,
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0x02000604
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}
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},
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},
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{
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.actim = 0xaafd478c,
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.actim1 = 0x91001f59,
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.actim05t = 0x000025e1,
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.conf1 = 0x00048403,
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.conf2 = 0x030000a9,
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.ddr2ctl = 0x000063b1,
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.gddr3ctl1 = 0x11000000,
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.misctl0 = 0x21000000,
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.pd_ctrl = 0xd1976442,
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.rkcfg = 0x002156c1,
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.test2_3 = 0xbfc70401,
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.test2_4 = 0x2801110d
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},
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{
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.cona = 0xa053a057,
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.conb = 0x17283544,
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.conc = 0x0a1a0b1a,
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.cond = 0x00000000,
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.cone = 0xffff0848,
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.conf = 0x08420000,
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.cong = 0x2b2b2a38,
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.conh = 0x00000000,
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.conm_1 = 0x40000500,
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.conm_2 = 0x400005ff,
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.mdct_1 = 0x80030303,
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.mdct_2 = 0x34220c3f,
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.test0 = 0xcccccccc,
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.test1 = 0xcccccccc,
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.testb = 0x00060124,
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.testc = 0x38470000,
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.testd = 0x00000000,
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.arba = 0x7f077a49,
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.arbc = 0xa0a070dd,
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.arbd = 0x07007046,
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.arbe = 0x40407046,
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.arbf = 0xa0a070c6,
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.arbg = 0xffff7047,
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.arbi = 0x20406188,
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.arbj = 0x9719595e,
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.arbk = 0x64f3fc79,
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.slct_1 = 0x00010800,
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.slct_2 = 0xff03ff00,
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.bmen = 0x00ff0001
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},
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{
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.mrs_1 = 0x00830001,
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.mrs_2 = 0x001c0002,
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.mrs_3 = 0x00010003,
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.mrs_10 = 0x00ff000a,
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.mrs_11 = 0x0000000b,
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.mrs_63 = 0x0000003f
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},
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.type = TYPE_LPDDR3,
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.dram_freq = 896 * MHz,
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},
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Reference in a new issue