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1. fix dtc to properly put @x,y in hex, not decimal.

Browse source 
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-07-30 15:08:25 +00:00
parent 96914e1655
commit 2f5d7b66a9
8 changed files with 38 additions and 25 deletions
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4
mainboard/adl/msm800sev/dts
View file

@ -37,11 +37,11 @@
pci@1,1 { pci@1,1 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
enable_ide = "1"; enable_ide = "1";
}; };
ioport@46 { ioport@2e {
/config/("superio/winbond/w83627hf/dts"); /config/("superio/winbond/w83627hf/dts");
com1enable = "1"; com1enable = "1";
}; };

6
mainboard/amd/db800/dts
View file

@ -34,7 +34,7 @@
pci@1,0 { pci@1,0 {
/config/("northbridge/amd/geodelx/pci"); /config/("northbridge/amd/geodelx/pci");
}; };
pci@15,0 { pci@f,0 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus. /* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */ * Each bit is an IRQ 0-15. */
@ -48,11 +48,11 @@
enable_gpio_int_route = "0x0D0C0700"; enable_gpio_int_route = "0x0D0C0700";
enable_USBP4_device = "1"; enable_USBP4_device = "1";
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
enable_ide = "1"; enable_ide = "1";
}; };
ioport@46 { ioport@2e {
/config/("superio/winbond/w83627hf/dts"); /config/("superio/winbond/w83627hf/dts");
com1enable = "1"; com1enable = "1";
}; };

4
mainboard/amd/norwich/dts
View file

@ -34,7 +34,7 @@
pci@1,0 { pci@1,0 {
/config/("northbridge/amd/geodelx/pci"); /config/("northbridge/amd/geodelx/pci");
}; };
pci@15,0 { pci@f,0 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus. /* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */ * Each bit is an IRQ 0-15. */
@ -51,7 +51,7 @@
com1_address = "0x3f8"; com1_address = "0x3f8";
com1_irq = "4"; com1_irq = "4";
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
enable_ide = "1"; enable_ide = "1";
}; };

4
mainboard/artecgroup/dbe61/dts
View file

@ -89,7 +89,7 @@ end
pci@1,0 { pci@1,0 {
/config/("northbridge/amd/geodelx/pci"); /config/("northbridge/amd/geodelx/pci");
}; };
pci@15,0 { pci@f,0 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus. /* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */ * Each bit is an IRQ 0-15. */
@ -110,7 +110,7 @@ end
com2_address = "0x3f8"; com2_address = "0x3f8";
com2_irq = "4"; com2_irq = "4";
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
}; };
}; };

6
mainboard/artecgroup/dbe62/dts
View file

@ -28,11 +28,11 @@
domain@0 { domain@0 {
/config/("northbridge/amd/geodelx/domain"); /config/("northbridge/amd/geodelx/domain");
/* Video RAM has to be in 2MB chunks. */ /* Video RAM has to be in 2MB chunks. */
geode_video_mb = "8"; geode_video_mb = "16";
pci@1,0 { pci@1,0 {
/config/("northbridge/amd/geodelx/pci"); /config/("northbridge/amd/geodelx/pci");
}; };
pci@15,0 { pci@f,0 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus. /* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */ * Each bit is an IRQ 0-15. */
@ -55,7 +55,7 @@
/* USB Port Power Handling setting. */ /* USB Port Power Handling setting. */
pph = "0xf5"; pph = "0xf5";
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
}; };
}; };

6
mainboard/pcengines/alix1c/dts
View file

@ -32,7 +32,7 @@
pci@1,0 { pci@1,0 {
/config/("northbridge/amd/geodelx/pci"); /config/("northbridge/amd/geodelx/pci");
}; };
pci@15,0 { pci@f,0 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus. /* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */ * Each bit is an IRQ 0-15. */
@ -45,11 +45,11 @@
* See virtual PIC spec. */ * See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700"; enable_gpio_int_route = "0x0D0C0700";
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
enable_ide = "1"; enable_ide = "1";
}; };
ioport@46 { ioport@2e {
/config/("superio/winbond/w83627hf/dts"); /config/("superio/winbond/w83627hf/dts");
com1enable = "1"; com1enable = "1";
}; };

4
mainboard/pcengines/alix2c3/dts
View file

@ -30,7 +30,7 @@
pci@1,0 { pci@1,0 {
/config/("northbridge/amd/geodelx/pci"); /config/("northbridge/amd/geodelx/pci");
}; };
pci@15,0 { pci@f,0 {
/config/("southbridge/amd/cs5536/dts"); /config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus. /* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */ * Each bit is an IRQ 0-15. */
@ -49,7 +49,7 @@
/* this board does not really have vga; disable it (pci device 00:01.1) */ /* this board does not really have vga; disable it (pci device 00:01.1) */
unwanted_vpci = < 80000900 0 >; unwanted_vpci = < 80000900 0 >;
}; };
pci@15,2 { pci@f,2 {
/config/("southbridge/amd/cs5536/ide"); /config/("southbridge/amd/cs5536/ide");
enable_ide = "1"; enable_ide = "1";
}; };

29
util/dtc/flattree.c
View file

@ -551,27 +551,40 @@ static void coreboot_emit_special(FILE *e, struct node *tree)
if (path && path[1]) { if (path && path[1]) {
path++; path++;
if (!strncmp(tree->name, "cpu", 3)){ if (!strncmp(tree->name, "cpu", 3)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={ .id = %s }}},\n", fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={ .id = 0x%s }}},\n",
path); path);
} }
if (!strncmp(tree->name, "bus", 3)){ if (!strncmp(tree->name, "bus", 3)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = %s }}},\n", fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n",
path); path);
} }
if (!strncmp(tree->name, "apic", 4)){ if (!strncmp(tree->name, "apic", 4)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,.u={.apic={ %s }}},\n", fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n",
path); path);
} }
if (!strncmp(tree->name, "domain", 6)){ if (!strncmp(tree->name, "domain", 6)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = %s }}},\n", fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n",
path); path);
} }
if (!strncmp(tree->name, "pci", 3)){ if (!strncmp(tree->name, "pci", 3)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(%s)}}},\n", /* it's in two parts */
path); char *devfn = strdup(path);
char *dev = devfn;
char *fn;
fn = index(devfn, ',');
/* if there is no fn we assume 0 */
/* the Rules are unclear on this point */
if (fn)
*fn++ = 0;
else
fn = "0";
fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n",
dev, fn);
} }
if (!strncmp(tree->name, "ioport", 3)){ if (!strncmp(tree->name, "ioport", 6)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=%s}}},\n", fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n",
path); path);
} }
} }