From 2ef41ce236ab6aa70c95d6dc390aed24f91559a2 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 12 Dec 2016 13:57:11 -0600 Subject: [PATCH] UPSTREAM: vendorcode/google/chromeos: provide acpi phase enforcement pin macros In the factory it's helpful for knowing when a system being built is meant for release with all the security features locked down. Provide support for exporting this type of pin in the acpi tables. BUG=chrome-os-partner:59951 BRANCH=reef TEST=None Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/17802 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Change-Id: Iec70249f19fc36e5c9c3a05b1395f84a3bcda9d0 Reviewed-on: https://chromium-review.googlesource.com/420830 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Furquan Shaikh --- src/vendorcode/google/chromeos/chromeos.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index fd845bfae1..722d62eed5 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -76,6 +76,7 @@ enum { CROS_GPIO_REC = 1, /* Recovery */ CROS_GPIO_DEV = 2, /* Developer */ CROS_GPIO_WP = 3, /* Write Protect */ + CROS_GPIO_PE = 4, /* Phase enforcement for final product */ CROS_GPIO_ACTIVE_LOW = 0, CROS_GPIO_ACTIVE_HIGH = 1, @@ -125,4 +126,13 @@ struct cros_gpio { #define CROS_GPIO_WP_AH(num, dev) \ CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) +#define CROS_GPIO_PE_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_PE, pol, num, dev) + +#define CROS_GPIO_PE_AL(num, dev) \ + CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_PE_AH(num, dev) \ + CROS_GPIO_PE_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + #endif /* __CHROMEOS_H__ */