Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: northbridge/amd: Modify 00670F00 chip.h to match DCT

Browse source 
The Stoney device supports only a single channel of DRAM with
two DIMMs.  Correct the dimmensions of the SPD lookup array.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209
Reviewed-on: https://chromium-review.googlesource.com/407187
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2016-10-08 09:12:27 -06:00 • committed by chrome-bot
parent 963d2f8588
commit 2b3dc94dae
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/northbridge/amd/pi/00670F00/chip.h
View file

@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -18,7 +19,7 @@
struct northbridge_amd_pi_00670F00_config
{
u8 spdAddrLookup[2][2][4];
u8 spdAddrLookup[1][1][2];
};
#endif