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UPSTREAM: aopen/dxplplusu: Switch to 2MiB flash
BUG=none
BRANCH=none
TEST=none
Change-Id: I19800c852a27daf0aa301f07763ef8332464867a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9bafa2947b
Original-Change-Id: Iedc15823dc24b3211fe7954cdf4302934a517afb
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/17919
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/428269
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
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@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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# select PIRQ_ROUTE
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# select PIRQ_ROUTE
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select UDELAY_TSC
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select UDELAY_TSC
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_512
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select BOARD_ROMSIZE_KB_2048
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# select HW_SCRUBBER
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# select HW_SCRUBBER
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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