mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
will mainboards
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
abf9fea4a0
commit
22489894e1
16 changed files with 2006 additions and 0 deletions
300
src/mainboard/Iwill/DK8S2/Config.lb
Normal file
300
src/mainboard/Iwill/DK8S2/Config.lb
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@ -0,0 +1,300 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses HAVE_FALLBACK_BOOT
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uses HAVE_HARD_RESET
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uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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uses STACK_SIZE
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uses HEAP_SIZE
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uses USE_OPTION_TABLE
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE=524288
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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default HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=9
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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default HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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default HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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default CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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#default MAINBOARD_PART_NUMBER="HDAMA"
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#default MAINBOARD_VENDOR="ARIMA"
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###
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### LinuxBIOS layout values
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###
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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default STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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#cpu k8 end
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##
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## Build the objects we have code for in this directory.
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##
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#object mainboard.o
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driver mainboard.o
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/k8/earlymtrr.inc
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131" link 0
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111" link 0
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pci 0:0.0
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pci 0:1.0 on
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pci 0:1.1 on
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pci 0:1.2 on
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pci 0:1.3 on
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pci 0:1.5 off
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pci 0:1.6 off
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 off
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superio winbond/w83627thf link 1
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pnp 2e.0
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pnp 2e.1
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pnp 2e.2
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pnp 2e.3
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pnp 2e.4
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pnp 2e.5
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pnp 2e.6
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pnp 2e.7
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pnp 2e.8
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pnp 2e.9
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pnp 2e.a
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register "com1" = "{1, 0, 0x3f8, 4}"
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register "lpt" = "{1}"
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end
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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cpu k8 "cpu0"
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register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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end
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cpu k8 "cpu1"
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end
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##
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## Include the old serial code for those few places that still need it.
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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257
src/mainboard/Iwill/DK8S2/auto.c
Normal file
257
src/mainboard/Iwill/DK8S2/auto.c
Normal file
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@ -0,0 +1,257 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#define SIO_BASE 0x2e
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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|
else {
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/* Ensure the CPU has controll of the memory lines */
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||||||
|
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void memreset(int controllers, const struct mem_controller *ctrl)
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||||||
|
{
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||||||
|
if (is_cpu_pre_c0()) {
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udelay(800);
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||||||
|
/* Set memreset_high */
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|
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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||||||
|
udelay(90);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||||
|
{
|
||||||
|
/* Routing Table Node i
|
||||||
|
*
|
||||||
|
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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||||||
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* i: 0, 1, 2, 3, 4, 5, 6, 7
|
||||||
|
*
|
||||||
|
* [ 0: 3] Request Route
|
||||||
|
* [0] Route to this node
|
||||||
|
* [1] Route to Link 0
|
||||||
|
* [2] Route to Link 1
|
||||||
|
* [3] Route to Link 2
|
||||||
|
* [11: 8] Response Route
|
||||||
|
* [0] Route to this node
|
||||||
|
* [1] Route to Link 0
|
||||||
|
* [2] Route to Link 1
|
||||||
|
* [3] Route to Link 2
|
||||||
|
* [19:16] Broadcast route
|
||||||
|
* [0] Route to this node
|
||||||
|
* [1] Route to Link 0
|
||||||
|
* [2] Route to Link 1
|
||||||
|
* [3] Route to Link 2
|
||||||
|
*/
|
||||||
|
|
||||||
|
uint32_t ret=0x00010101; /* default row entry */
|
||||||
|
|
||||||
|
static const unsigned int rows_2p[2][2] = {
|
||||||
|
{ 0x00050101, 0x00010404 },
|
||||||
|
{ 0x00010404, 0x00050101 }
|
||||||
|
};
|
||||||
|
|
||||||
|
if(maxnodes>2) {
|
||||||
|
print_debug("this mainboard is only designed for 2 cpus\r\n");
|
||||||
|
maxnodes=2;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
if (!(node>=maxnodes || row>=maxnodes)) {
|
||||||
|
ret=rows_2p[node][row];
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||||
|
{
|
||||||
|
/* nothing to do */
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
|
{
|
||||||
|
return smbus_read_byte(device, address);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* no specific code here. this should go away completely */
|
||||||
|
static void coherent_ht_mainboard(unsigned cpus)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
#include "northbridge/amd/amdk8/raminit.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
|
#include "sdram/generic_sdram.c"
|
||||||
|
|
||||||
|
static void enable_lapic(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
msr_t msr;
|
||||||
|
msr = rdmsr(0x1b);
|
||||||
|
msr.hi &= 0xffffff00;
|
||||||
|
msr.lo &= 0x000007ff;
|
||||||
|
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
|
||||||
|
wrmsr(0x1b, msr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stop_this_cpu(void)
|
||||||
|
{
|
||||||
|
unsigned apicid;
|
||||||
|
apicid = apic_read(APIC_ID) >> 24;
|
||||||
|
|
||||||
|
/* Send an APIC INIT to myself */
|
||||||
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
||||||
|
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
|
||||||
|
/* Wait for the ipi send to finish */
|
||||||
|
apic_wait_icr_idle();
|
||||||
|
|
||||||
|
/* Deassert the APIC INIT */
|
||||||
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
||||||
|
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
|
||||||
|
/* Wait for the ipi send to finish */
|
||||||
|
apic_wait_icr_idle();
|
||||||
|
|
||||||
|
/* If I haven't halted spin forever */
|
||||||
|
for(;;) {
|
||||||
|
hlt();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PC87360_FDC 0x00
|
||||||
|
#define PC87360_PP 0x01
|
||||||
|
#define PC87360_SP2 0x02
|
||||||
|
#define PC87360_SP1 0x03
|
||||||
|
#define PC87360_SWC 0x04
|
||||||
|
#define PC87360_KBCM 0x05
|
||||||
|
#define PC87360_KBCK 0x06
|
||||||
|
#define PC87360_GPIO 0x07
|
||||||
|
#define PC87360_ACB 0x08
|
||||||
|
#define PC87360_FSCM 0x09
|
||||||
|
#define PC87360_WDT 0x0A
|
||||||
|
|
||||||
|
static void pc87360_enable_serial(void)
|
||||||
|
{
|
||||||
|
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
|
||||||
|
pnp_set_enable(SIO_BASE, 1);
|
||||||
|
pnp_set_iobase0(SIO_BASE, 0x3f8);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define FIRST_CPU 1
|
||||||
|
#define SECOND_CPU 1
|
||||||
|
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||||
|
static void main(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* GPIO28 of 8111 will control H0_MEMRESET_L
|
||||||
|
* GPIO29 of 8111 will control H1_MEMRESET_L
|
||||||
|
*/
|
||||||
|
static const struct mem_controller cpu[] = {
|
||||||
|
#if FIRST_CPU
|
||||||
|
{
|
||||||
|
.node_id = 0,
|
||||||
|
.f0 = PCI_DEV(0, 0x18, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x18, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x18, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x18, 3),
|
||||||
|
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||||
|
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if SECOND_CPU
|
||||||
|
{
|
||||||
|
.node_id = 1,
|
||||||
|
.f0 = PCI_DEV(0, 0x19, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x19, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x19, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x19, 3),
|
||||||
|
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||||
|
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
enable_lapic();
|
||||||
|
init_timer();
|
||||||
|
if (!boot_cpu()) {
|
||||||
|
stop_this_cpu();
|
||||||
|
}
|
||||||
|
pc87360_enable_serial();
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
setup_default_resource_map();
|
||||||
|
setup_coherent_ht_domain();
|
||||||
|
enumerate_ht_chain(0);
|
||||||
|
distinguish_cpu_resets(0);
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
print_pci_devices();
|
||||||
|
#endif
|
||||||
|
enable_smbus();
|
||||||
|
#if 0
|
||||||
|
dump_spd_registers(&cpu[0]);
|
||||||
|
#endif
|
||||||
|
memreset_setup();
|
||||||
|
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
dump_pci_devices();
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
dump_pci_device(PCI_DEV(0, 0x18, 2));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check all of memory */
|
||||||
|
#if 0
|
||||||
|
msr_t msr;
|
||||||
|
msr = rdmsr(TOP_MEM);
|
||||||
|
print_debug("TOP_MEM: ");
|
||||||
|
print_debug_hex32(msr.hi);
|
||||||
|
print_debug_hex32(msr.lo);
|
||||||
|
print_debug("\r\n");
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
ram_check(0x00000000, msr.lo);
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
static const struct {
|
||||||
|
unsigned long lo, hi;
|
||||||
|
} check_addrs[] = {
|
||||||
|
/* Check 16MB of memory @ 0*/
|
||||||
|
{ 0x00000000, 0x01000000 },
|
||||||
|
#if TOTAL_CPUS > 1
|
||||||
|
/* Check 16MB of memory @ 2GB */
|
||||||
|
{ 0x80000000, 0x81000000 },
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
int i;
|
||||||
|
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
|
||||||
|
ram_check(check_addrs[i].lo, check_addrs[i].hi);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
5
src/mainboard/Iwill/DK8S2/chip.h
Normal file
5
src/mainboard/Iwill/DK8S2/chip.h
Normal file
|
|
@ -0,0 +1,5 @@
|
||||||
|
struct chip_control mainboard_arima_hdama_control;
|
||||||
|
|
||||||
|
struct mainboard_arima_hdama_config {
|
||||||
|
int nothing;
|
||||||
|
};
|
||||||
74
src/mainboard/Iwill/DK8S2/cmos.layout
Normal file
74
src/mainboard/Iwill/DK8S2/cmos.layout
Normal file
|
|
@ -0,0 +1,74 @@
|
||||||
|
entries
|
||||||
|
|
||||||
|
#start-bit length config config-ID name
|
||||||
|
#0 8 r 0 seconds
|
||||||
|
#8 8 r 0 alarm_seconds
|
||||||
|
#16 8 r 0 minutes
|
||||||
|
#24 8 r 0 alarm_minutes
|
||||||
|
#32 8 r 0 hours
|
||||||
|
#40 8 r 0 alarm_hours
|
||||||
|
#48 8 r 0 day_of_week
|
||||||
|
#56 8 r 0 day_of_month
|
||||||
|
#64 8 r 0 month
|
||||||
|
#72 8 r 0 year
|
||||||
|
#80 4 r 0 rate_select
|
||||||
|
#84 3 r 0 REF_Clock
|
||||||
|
#87 1 r 0 UIP
|
||||||
|
#88 1 r 0 auto_switch_DST
|
||||||
|
#89 1 r 0 24_hour_mode
|
||||||
|
#90 1 r 0 binary_values_enable
|
||||||
|
#91 1 r 0 square-wave_out_enable
|
||||||
|
#92 1 r 0 update_finished_enable
|
||||||
|
#93 1 r 0 alarm_interrupt_enable
|
||||||
|
#94 1 r 0 periodic_interrupt_enable
|
||||||
|
#95 1 r 0 disable_clock_updates
|
||||||
|
#96 288 r 0 temporary_filler
|
||||||
|
0 384 r 0 reserved_memory
|
||||||
|
384 1 e 4 boot_option
|
||||||
|
385 1 e 4 last_boot
|
||||||
|
386 1 e 1 ECC_memory
|
||||||
|
388 4 r 0 reboot_bits
|
||||||
|
392 3 e 5 baud_rate
|
||||||
|
400 1 e 1 power_on_after_fail
|
||||||
|
412 4 e 6 debug_level
|
||||||
|
416 4 e 7 boot_first
|
||||||
|
420 4 e 7 boot_second
|
||||||
|
424 4 e 7 boot_third
|
||||||
|
428 4 h 0 boot_index
|
||||||
|
432 8 h 0 boot_countdown
|
||||||
|
1008 16 h 0 check_sum
|
||||||
|
|
||||||
|
enumerations
|
||||||
|
|
||||||
|
#ID value text
|
||||||
|
1 0 Disable
|
||||||
|
1 1 Enable
|
||||||
|
2 0 Enable
|
||||||
|
2 1 Disable
|
||||||
|
4 0 Fallback
|
||||||
|
4 1 Normal
|
||||||
|
5 0 115200
|
||||||
|
5 1 57600
|
||||||
|
5 2 38400
|
||||||
|
5 3 19200
|
||||||
|
5 4 9600
|
||||||
|
5 5 4800
|
||||||
|
5 6 2400
|
||||||
|
5 7 1200
|
||||||
|
6 6 Notice
|
||||||
|
6 7 Info
|
||||||
|
6 8 Debug
|
||||||
|
6 9 Spew
|
||||||
|
7 0 Network
|
||||||
|
7 1 HDD
|
||||||
|
7 2 Floppy
|
||||||
|
7 8 Fallback_Network
|
||||||
|
7 9 Fallback_HDD
|
||||||
|
7 10 Fallback_Floppy
|
||||||
|
#7 3 ROM
|
||||||
|
|
||||||
|
checksums
|
||||||
|
|
||||||
|
checksum 392 1007 1008
|
||||||
|
|
||||||
|
|
||||||
42
src/mainboard/Iwill/DK8S2/failover.c
Normal file
42
src/mainboard/Iwill/DK8S2/failover.c
Normal file
|
|
@ -0,0 +1,42 @@
|
||||||
|
#define ASSEMBLY 1
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include "arch/romcc_io.h"
|
||||||
|
#include "pc80/mc146818rtc_early.c"
|
||||||
|
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||||
|
#include "northbridge/amd/amdk8/early_ht.c"
|
||||||
|
#include "cpu/p6/boot_cpu.c"
|
||||||
|
#include "northbridge/amd/amdk8/reset_test.c"
|
||||||
|
|
||||||
|
static void main(void)
|
||||||
|
{
|
||||||
|
/* Nothing special needs to be done to find bus 0 */
|
||||||
|
/* Allow the HT devices to be found */
|
||||||
|
enumerate_ht_chain(0);
|
||||||
|
|
||||||
|
/* Setup the 8111 */
|
||||||
|
amd8111_enable_rom();
|
||||||
|
|
||||||
|
/* Is this a cpu reset? */
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
if (last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
} else {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Is this a deliberate reset by the bios */
|
||||||
|
else if (bios_reset_detected() && last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
/* Is this a secondary cpu? */
|
||||||
|
else if (!boot_cpu() && last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
/* This is the primary cpu how should I boot? */
|
||||||
|
else if (do_normal_boot()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
}
|
||||||
52
src/mainboard/Iwill/DK8S2/irq_tables.c
Normal file
52
src/mainboard/Iwill/DK8S2/irq_tables.c
Normal file
|
|
@ -0,0 +1,52 @@
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
|
||||||
|
#define IRQ_ROUTER_BUS 1
|
||||||
|
#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
|
||||||
|
#define IRQ_ROUTER_VENDOR 0x1022
|
||||||
|
#define IRQ_ROUTER_DEVICE 0x746b
|
||||||
|
|
||||||
|
#define AVAILABLE_IRQS 0xdef8
|
||||||
|
#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
|
||||||
|
{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
|
||||||
|
{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
|
||||||
|
|
||||||
|
/* Each IRQ_SLOT entry consists of:
|
||||||
|
* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
|
||||||
|
*/
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
|
||||||
|
* devices on the bus */
|
||||||
|
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
|
||||||
|
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
|
||||||
|
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
IRQ_ROUTER_VENDOR, /* Vendor */
|
||||||
|
IRQ_ROUTER_DEVICE, /* Device */
|
||||||
|
0x00, /* Crap (miniport) */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0x00, /* u8 checksum , mod 256 checksum must give
|
||||||
|
* zero, will be corrected later
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
|
||||||
|
/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
|
||||||
|
|
||||||
|
/* PCI Slot 1-6 */
|
||||||
|
IRQ_SLOT (1, 3,1,0, 2,3,4,1 ),
|
||||||
|
IRQ_SLOT (2, 3,2,0, 3,4,1,2 ),
|
||||||
|
IRQ_SLOT (3, 2,1,0, 2,3,4,1 ),
|
||||||
|
IRQ_SLOT (4, 2,2,0, 3,4,1,2 ),
|
||||||
|
IRQ_SLOT (5, 4,5,0, 2,3,4,1 ),
|
||||||
|
IRQ_SLOT (6, 4,4,0, 1,2,3,4 ),
|
||||||
|
|
||||||
|
/* Onboard NICs */
|
||||||
|
IRQ_SLOT (0, 2,3,0, 4,0,0,0 ),
|
||||||
|
IRQ_SLOT (0, 2,4,0, 4,0,0,0 ),
|
||||||
|
|
||||||
|
/* Let Linux know about bus 1 */
|
||||||
|
IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
|
||||||
|
}
|
||||||
|
};
|
||||||
41
src/mainboard/Iwill/DK8S2/mainboard.c
Normal file
41
src/mainboard/Iwill/DK8S2/mainboard.c
Normal file
|
|
@ -0,0 +1,41 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/chip.h>
|
||||||
|
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
|
||||||
|
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||||
|
{
|
||||||
|
0, 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct device_operations mainboard_operations = {
|
||||||
|
.read_resources = root_dev_read_resources,
|
||||||
|
.set_resources = root_dev_set_resources,
|
||||||
|
.enable_resources = enable_childrens_resources,
|
||||||
|
.init = 0,
|
||||||
|
.scan_bus = amdk8_scan_root_bus,
|
||||||
|
.enable = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enumerate(struct chip *chip)
|
||||||
|
{
|
||||||
|
struct chip *child;
|
||||||
|
dev_root.ops = &mainboard_operations;
|
||||||
|
chip->dev = &dev_root;
|
||||||
|
chip->bus = 0;
|
||||||
|
for(child = chip->children; child; child = child->next) {
|
||||||
|
child->bus = &dev_root.link[0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
struct chip_control mainboard_arima_hdama_control = {
|
||||||
|
.enumerate = enumerate,
|
||||||
|
.name = "Arima HDAMA mainboard ",
|
||||||
|
};
|
||||||
|
|
||||||
232
src/mainboard/Iwill/DK8S2/mptable.c
Normal file
232
src/mainboard/Iwill/DK8S2/mptable.c
Normal file
|
|
@ -0,0 +1,232 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/smp/mpspec.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||||
|
{
|
||||||
|
static const char sig[4] = "PCMP";
|
||||||
|
static const char oem[8] = "LNXI ";
|
||||||
|
static const char productid[12] = "HDAMA ";
|
||||||
|
struct mp_config_table *mc;
|
||||||
|
unsigned char bus_num;
|
||||||
|
unsigned char bus_isa;
|
||||||
|
unsigned char bus_8131_1;
|
||||||
|
unsigned char bus_8131_2;
|
||||||
|
unsigned char bus_8111_1;
|
||||||
|
|
||||||
|
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||||
|
memset(mc, 0, sizeof(*mc));
|
||||||
|
|
||||||
|
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||||
|
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||||
|
mc->mpc_spec = 0x04;
|
||||||
|
mc->mpc_checksum = 0; /* not yet computed */
|
||||||
|
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||||
|
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||||
|
mc->mpc_oemptr = 0;
|
||||||
|
mc->mpc_oemsize = 0;
|
||||||
|
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||||
|
mc->mpc_lapic = LAPIC_ADDR;
|
||||||
|
mc->mpe_length = 0;
|
||||||
|
mc->mpe_checksum = 0;
|
||||||
|
mc->reserved = 0;
|
||||||
|
|
||||||
|
smp_write_processors(mc, processor_map);
|
||||||
|
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
|
||||||
|
/* 8111 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_isa++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8111_1 = 4;
|
||||||
|
bus_isa = 5;
|
||||||
|
}
|
||||||
|
/* 8131-1 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_1 = 2;
|
||||||
|
}
|
||||||
|
/* 8131-2 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_2 = 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* define bus and isa numbers */
|
||||||
|
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||||
|
smp_write_bus(mc, bus_num, "PCI ");
|
||||||
|
}
|
||||||
|
smp_write_bus(mc, bus_isa, "ISA ");
|
||||||
|
|
||||||
|
/* IOAPIC handling */
|
||||||
|
|
||||||
|
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
uint32_t base;
|
||||||
|
/* 8131 apic 3 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
|
||||||
|
if (dev) {
|
||||||
|
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||||
|
smp_write_ioapic(mc, 0x03, 0x11, base);
|
||||||
|
}
|
||||||
|
/* 8131 apic 4 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
|
||||||
|
if (dev) {
|
||||||
|
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||||
|
smp_write_ioapic(mc, 0x04, 0x11, base);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ISA backward compatibility interrupts */
|
||||||
|
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, 0x02, 0x00);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x01, 0x02, 0x01);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, 0x02, 0x02);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x03, 0x02, 0x03);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x04, 0x02, 0x04);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x05, 0x02, 0x05);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x06, 0x02, 0x06);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x07, 0x02, 0x07);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x08, 0x02, 0x08);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x09, 0x02, 0x09);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0a, 0x02, 0x0a);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0b, 0x02, 0x0b);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0c, 0x02, 0x0c);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0d, 0x02, 0x0d);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0e, 0x02, 0x0e);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0f, 0x02, 0x0f);
|
||||||
|
|
||||||
|
/* Standard local interrupt assignments */
|
||||||
|
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||||
|
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||||
|
|
||||||
|
|
||||||
|
/* PCI Slot 1 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|0, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|1, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|2, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|3, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 2 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|0, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|1, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|2, 0x02, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|3, 0x02, 0x11);
|
||||||
|
|
||||||
|
/* PCI Slot 3 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|0, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|1, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|2, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|3, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 4 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|0, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|1, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|2, 0x02, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|3, 0x02, 0x11);
|
||||||
|
|
||||||
|
/* PCI Slot 5 */
|
||||||
|
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|0, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|1, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|2, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|3, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 6 */
|
||||||
|
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|0, 0x02, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|1, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|2, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|3, 0x02, 0x13);
|
||||||
|
|
||||||
|
/* On board nics */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (3<<2)|0, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (4<<2)|0, 0x02, 0x13);
|
||||||
|
|
||||||
|
/* There is no extension information... */
|
||||||
|
|
||||||
|
/* Compute the checksums */
|
||||||
|
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||||
|
|
||||||
|
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||||
|
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||||
|
mc, smp_next_mpe_entry(mc));
|
||||||
|
return smp_next_mpe_entry(mc);
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||||
|
{
|
||||||
|
void *v;
|
||||||
|
v = smp_write_floating_table(addr);
|
||||||
|
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||||
|
}
|
||||||
|
|
||||||
300
src/mainboard/Iwill/DK8X/Config.lb
Normal file
300
src/mainboard/Iwill/DK8X/Config.lb
Normal file
|
|
@ -0,0 +1,300 @@
|
||||||
|
uses HAVE_MP_TABLE
|
||||||
|
uses HAVE_PIRQ_TABLE
|
||||||
|
uses USE_FALLBACK_IMAGE
|
||||||
|
uses HAVE_FALLBACK_BOOT
|
||||||
|
uses HAVE_HARD_RESET
|
||||||
|
uses IRQ_SLOT_COUNT
|
||||||
|
uses HAVE_OPTION_TABLE
|
||||||
|
uses CONFIG_MAX_CPUS
|
||||||
|
uses CONFIG_IOAPIC
|
||||||
|
uses CONFIG_SMP
|
||||||
|
uses FALLBACK_SIZE
|
||||||
|
uses ROM_SIZE
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_IMAGE_SIZE
|
||||||
|
uses ROM_SECTION_SIZE
|
||||||
|
uses ROM_SECTION_OFFSET
|
||||||
|
uses CONFIG_ROM_STREAM
|
||||||
|
uses CONFIG_ROM_STREAM_START
|
||||||
|
uses PAYLOAD_SIZE
|
||||||
|
uses _ROMBASE
|
||||||
|
uses XIP_ROM_SIZE
|
||||||
|
uses XIP_ROM_BASE
|
||||||
|
uses STACK_SIZE
|
||||||
|
uses HEAP_SIZE
|
||||||
|
uses USE_OPTION_TABLE
|
||||||
|
|
||||||
|
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||||
|
default ROM_SIZE=524288
|
||||||
|
|
||||||
|
###
|
||||||
|
### Build options
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code for the fallback boot
|
||||||
|
##
|
||||||
|
default HAVE_FALLBACK_BOOT=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to reset the motherboard from linuxBIOS
|
||||||
|
##
|
||||||
|
default HAVE_HARD_RESET=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a programmable irq routing table
|
||||||
|
##
|
||||||
|
default HAVE_PIRQ_TABLE=1
|
||||||
|
default IRQ_SLOT_COUNT=9
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export an x86 MP table
|
||||||
|
## Useful for specifying IRQ routing values
|
||||||
|
##
|
||||||
|
default HAVE_MP_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to export a CMOS option table
|
||||||
|
##
|
||||||
|
default HAVE_OPTION_TABLE=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code for SMP support
|
||||||
|
## Only worry about 2 micro processors
|
||||||
|
##
|
||||||
|
default CONFIG_SMP=1
|
||||||
|
default CONFIG_MAX_CPUS=2
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build code to setup a generic IOAPIC
|
||||||
|
##
|
||||||
|
default CONFIG_IOAPIC=1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Clean up the motherboard id strings
|
||||||
|
##
|
||||||
|
#default MAINBOARD_PART_NUMBER="HDAMA"
|
||||||
|
#default MAINBOARD_VENDOR="ARIMA"
|
||||||
|
|
||||||
|
###
|
||||||
|
### LinuxBIOS layout values
|
||||||
|
###
|
||||||
|
|
||||||
|
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||||
|
default ROM_IMAGE_SIZE = 65536
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 8K stack
|
||||||
|
##
|
||||||
|
default STACK_SIZE=0x2000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Use a small 16K heap
|
||||||
|
##
|
||||||
|
default HEAP_SIZE=0x4000
|
||||||
|
|
||||||
|
##
|
||||||
|
## Only use the option table in a normal image
|
||||||
|
##
|
||||||
|
default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||||
|
|
||||||
|
##
|
||||||
|
## Compute the location and size of where this firmware image
|
||||||
|
## (linuxBIOS plus bootloader) will live in the boot rom chip.
|
||||||
|
##
|
||||||
|
if USE_FALLBACK_IMAGE
|
||||||
|
default ROM_SECTION_SIZE = FALLBACK_SIZE
|
||||||
|
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
|
||||||
|
else
|
||||||
|
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
|
||||||
|
default ROM_SECTION_OFFSET = 0
|
||||||
|
end
|
||||||
|
|
||||||
|
##
|
||||||
|
## Compute the start location and size size of
|
||||||
|
## The linuxBIOS bootloader.
|
||||||
|
##
|
||||||
|
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
|
||||||
|
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
|
||||||
|
default CONFIG_ROM_STREAM = 1
|
||||||
|
|
||||||
|
##
|
||||||
|
## Compute where this copy of linuxBIOS will start in the boot rom
|
||||||
|
##
|
||||||
|
default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
|
||||||
|
|
||||||
|
##
|
||||||
|
## Compute a range of ROM that can cached to speed up linuxBIOS,
|
||||||
|
## execution speed.
|
||||||
|
##
|
||||||
|
## XIP_ROM_SIZE must be a power of 2.
|
||||||
|
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
|
||||||
|
##
|
||||||
|
default XIP_ROM_SIZE=65536
|
||||||
|
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
|
||||||
|
|
||||||
|
##
|
||||||
|
## Set all of the defaults for an x86 architecture
|
||||||
|
##
|
||||||
|
|
||||||
|
arch i386 end
|
||||||
|
#cpu k8 end
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build the objects we have code for in this directory.
|
||||||
|
##
|
||||||
|
|
||||||
|
#object mainboard.o
|
||||||
|
driver mainboard.o
|
||||||
|
#object static_devices.o
|
||||||
|
if HAVE_MP_TABLE object mptable.o end
|
||||||
|
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||||
|
object reset.o
|
||||||
|
|
||||||
|
##
|
||||||
|
## Romcc output
|
||||||
|
##
|
||||||
|
makerule ./failover.E
|
||||||
|
depends "$(MAINBOARD)/failover.c"
|
||||||
|
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
|
||||||
|
end
|
||||||
|
|
||||||
|
makerule ./failover.inc
|
||||||
|
depends "./failover.E ./romcc"
|
||||||
|
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
|
||||||
|
end
|
||||||
|
|
||||||
|
makerule ./auto.E
|
||||||
|
depends "$(MAINBOARD)/auto.c"
|
||||||
|
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
|
||||||
|
end
|
||||||
|
makerule ./auto.inc
|
||||||
|
depends "./auto.E ./romcc"
|
||||||
|
action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
|
||||||
|
end
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build our 16 bit and 32 bit linuxBIOS entry code
|
||||||
|
##
|
||||||
|
mainboardinit cpu/i386/entry16.inc
|
||||||
|
mainboardinit cpu/i386/entry32.inc
|
||||||
|
ldscript /cpu/i386/entry16.lds
|
||||||
|
ldscript /cpu/i386/entry32.lds
|
||||||
|
|
||||||
|
##
|
||||||
|
## Build our reset vector (This is where linuxBIOS is entered)
|
||||||
|
##
|
||||||
|
if USE_FALLBACK_IMAGE
|
||||||
|
mainboardinit cpu/i386/reset16.inc
|
||||||
|
ldscript /cpu/i386/reset16.lds
|
||||||
|
else
|
||||||
|
mainboardinit cpu/i386/reset32.inc
|
||||||
|
ldscript /cpu/i386/reset32.lds
|
||||||
|
end
|
||||||
|
|
||||||
|
### Should this be in the northbridge code?
|
||||||
|
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||||
|
|
||||||
|
##
|
||||||
|
## Include an id string (For safe flashing)
|
||||||
|
##
|
||||||
|
mainboardinit arch/i386/lib/id.inc
|
||||||
|
ldscript /arch/i386/lib/id.lds
|
||||||
|
|
||||||
|
##
|
||||||
|
## Setup our mtrrs
|
||||||
|
##
|
||||||
|
mainboardinit cpu/k8/earlymtrr.inc
|
||||||
|
|
||||||
|
###
|
||||||
|
### This is the early phase of linuxBIOS startup
|
||||||
|
### Things are delicate and we test to see if we should
|
||||||
|
### failover to another image.
|
||||||
|
###
|
||||||
|
if USE_FALLBACK_IMAGE
|
||||||
|
ldscript /arch/i386/lib/failover.lds
|
||||||
|
mainboardinit ./failover.inc
|
||||||
|
end
|
||||||
|
|
||||||
|
###
|
||||||
|
### O.k. We aren't just an intermediary anymore!
|
||||||
|
###
|
||||||
|
|
||||||
|
##
|
||||||
|
## Setup RAM
|
||||||
|
##
|
||||||
|
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||||
|
mainboardinit ./auto.inc
|
||||||
|
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||||
|
|
||||||
|
##
|
||||||
|
## Include the secondary Configuration files
|
||||||
|
##
|
||||||
|
dir /pc80
|
||||||
|
config chip.h
|
||||||
|
|
||||||
|
northbridge amd/amdk8 "mc0"
|
||||||
|
pci 0:18.0
|
||||||
|
pci 0:18.0
|
||||||
|
pci 0:18.0
|
||||||
|
pci 0:18.1
|
||||||
|
pci 0:18.2
|
||||||
|
pci 0:18.3
|
||||||
|
southbridge amd/amd8131 "amd8131" link 0
|
||||||
|
pci 0:0.0
|
||||||
|
pci 0:0.1
|
||||||
|
pci 0:1.0
|
||||||
|
pci 0:1.1
|
||||||
|
end
|
||||||
|
southbridge amd/amd8111 "amd8111" link 0
|
||||||
|
pci 0:0.0
|
||||||
|
pci 0:1.0 on
|
||||||
|
pci 0:1.1 on
|
||||||
|
pci 0:1.2 on
|
||||||
|
pci 0:1.3 on
|
||||||
|
pci 0:1.5 off
|
||||||
|
pci 0:1.6 off
|
||||||
|
pci 1:0.0 on
|
||||||
|
pci 1:0.1 on
|
||||||
|
pci 1:0.2 on
|
||||||
|
pci 1:1.0 off
|
||||||
|
superio winbond/w83627thf link 1
|
||||||
|
pnp 2e.0
|
||||||
|
pnp 2e.1
|
||||||
|
pnp 2e.2
|
||||||
|
pnp 2e.3
|
||||||
|
pnp 2e.4
|
||||||
|
pnp 2e.5
|
||||||
|
pnp 2e.6
|
||||||
|
pnp 2e.7
|
||||||
|
pnp 2e.8
|
||||||
|
pnp 2e.9
|
||||||
|
pnp 2e.a
|
||||||
|
register "com1" = "{1, 0, 0x3f8, 4}"
|
||||||
|
register "lpt" = "{1}"
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
northbridge amd/amdk8 "mc1"
|
||||||
|
pci 0:19.0
|
||||||
|
pci 0:19.0
|
||||||
|
pci 0:19.0
|
||||||
|
pci 0:19.1
|
||||||
|
pci 0:19.2
|
||||||
|
pci 0:19.3
|
||||||
|
end
|
||||||
|
|
||||||
|
cpu k8 "cpu0"
|
||||||
|
register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
|
||||||
|
end
|
||||||
|
|
||||||
|
cpu k8 "cpu1"
|
||||||
|
end
|
||||||
|
|
||||||
|
##
|
||||||
|
## Include the old serial code for those few places that still need it.
|
||||||
|
##
|
||||||
|
mainboardinit pc80/serial.inc
|
||||||
|
mainboardinit arch/i386/lib/console.inc
|
||||||
|
|
||||||
257
src/mainboard/Iwill/DK8X/auto.c
Normal file
257
src/mainboard/Iwill/DK8X/auto.c
Normal file
|
|
@ -0,0 +1,257 @@
|
||||||
|
#define ASSEMBLY 1
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <cpu/p6/apic.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/pnp.h>
|
||||||
|
#include <arch/romcc_io.h>
|
||||||
|
#include "pc80/serial.c"
|
||||||
|
#include "arch/i386/lib/console.c"
|
||||||
|
#include "ram/ramtest.c"
|
||||||
|
#include "northbridge/amd/amdk8/early_ht.c"
|
||||||
|
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
|
||||||
|
#include "northbridge/amd/amdk8/raminit.h"
|
||||||
|
#include "cpu/k8/apic_timer.c"
|
||||||
|
#include "lib/delay.c"
|
||||||
|
#include "cpu/p6/boot_cpu.c"
|
||||||
|
#include "northbridge/amd/amdk8/reset_test.c"
|
||||||
|
#include "debug.c"
|
||||||
|
#include "northbridge/amd/amdk8/cpu_rev.c"
|
||||||
|
|
||||||
|
#define SIO_BASE 0x2e
|
||||||
|
|
||||||
|
static void memreset_setup(void)
|
||||||
|
{
|
||||||
|
if (is_cpu_pre_c0()) {
|
||||||
|
/* Set the memreset low */
|
||||||
|
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
||||||
|
/* Ensure the BIOS has control of the memory lines */
|
||||||
|
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
/* Ensure the CPU has controll of the memory lines */
|
||||||
|
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
|
{
|
||||||
|
if (is_cpu_pre_c0()) {
|
||||||
|
udelay(800);
|
||||||
|
/* Set memreset_high */
|
||||||
|
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
|
||||||
|
udelay(90);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||||
|
{
|
||||||
|
/* Routing Table Node i
|
||||||
|
*
|
||||||
|
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
|
||||||
|
* i: 0, 1, 2, 3, 4, 5, 6, 7
|
||||||
|
*
|
||||||
|
* [ 0: 3] Request Route
|
||||||
|
* [0] Route to this node
|
||||||
|
* [1] Route to Link 0
|
||||||
|
* [2] Route to Link 1
|
||||||
|
* [3] Route to Link 2
|
||||||
|
* [11: 8] Response Route
|
||||||
|
* [0] Route to this node
|
||||||
|
* [1] Route to Link 0
|
||||||
|
* [2] Route to Link 1
|
||||||
|
* [3] Route to Link 2
|
||||||
|
* [19:16] Broadcast route
|
||||||
|
* [0] Route to this node
|
||||||
|
* [1] Route to Link 0
|
||||||
|
* [2] Route to Link 1
|
||||||
|
* [3] Route to Link 2
|
||||||
|
*/
|
||||||
|
|
||||||
|
uint32_t ret=0x00010101; /* default row entry */
|
||||||
|
|
||||||
|
static const unsigned int rows_2p[2][2] = {
|
||||||
|
{ 0x00050101, 0x00010404 },
|
||||||
|
{ 0x00010404, 0x00050101 }
|
||||||
|
};
|
||||||
|
|
||||||
|
if(maxnodes>2) {
|
||||||
|
print_debug("this mainboard is only designed for 2 cpus\r\n");
|
||||||
|
maxnodes=2;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
if (!(node>=maxnodes || row>=maxnodes)) {
|
||||||
|
ret=rows_2p[node][row];
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||||
|
{
|
||||||
|
/* nothing to do */
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
|
{
|
||||||
|
return smbus_read_byte(device, address);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* no specific code here. this should go away completely */
|
||||||
|
static void coherent_ht_mainboard(unsigned cpus)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
#include "northbridge/amd/amdk8/raminit.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
|
#include "sdram/generic_sdram.c"
|
||||||
|
|
||||||
|
static void enable_lapic(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
msr_t msr;
|
||||||
|
msr = rdmsr(0x1b);
|
||||||
|
msr.hi &= 0xffffff00;
|
||||||
|
msr.lo &= 0x000007ff;
|
||||||
|
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
|
||||||
|
wrmsr(0x1b, msr);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stop_this_cpu(void)
|
||||||
|
{
|
||||||
|
unsigned apicid;
|
||||||
|
apicid = apic_read(APIC_ID) >> 24;
|
||||||
|
|
||||||
|
/* Send an APIC INIT to myself */
|
||||||
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
||||||
|
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
|
||||||
|
/* Wait for the ipi send to finish */
|
||||||
|
apic_wait_icr_idle();
|
||||||
|
|
||||||
|
/* Deassert the APIC INIT */
|
||||||
|
apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
|
||||||
|
apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
|
||||||
|
/* Wait for the ipi send to finish */
|
||||||
|
apic_wait_icr_idle();
|
||||||
|
|
||||||
|
/* If I haven't halted spin forever */
|
||||||
|
for(;;) {
|
||||||
|
hlt();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#define PC87360_FDC 0x00
|
||||||
|
#define PC87360_PP 0x01
|
||||||
|
#define PC87360_SP2 0x02
|
||||||
|
#define PC87360_SP1 0x03
|
||||||
|
#define PC87360_SWC 0x04
|
||||||
|
#define PC87360_KBCM 0x05
|
||||||
|
#define PC87360_KBCK 0x06
|
||||||
|
#define PC87360_GPIO 0x07
|
||||||
|
#define PC87360_ACB 0x08
|
||||||
|
#define PC87360_FSCM 0x09
|
||||||
|
#define PC87360_WDT 0x0A
|
||||||
|
|
||||||
|
static void pc87360_enable_serial(void)
|
||||||
|
{
|
||||||
|
pnp_set_logical_device(SIO_BASE, PC87360_SP1);
|
||||||
|
pnp_set_enable(SIO_BASE, 1);
|
||||||
|
pnp_set_iobase0(SIO_BASE, 0x3f8);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define FIRST_CPU 1
|
||||||
|
#define SECOND_CPU 1
|
||||||
|
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||||
|
static void main(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* GPIO28 of 8111 will control H0_MEMRESET_L
|
||||||
|
* GPIO29 of 8111 will control H1_MEMRESET_L
|
||||||
|
*/
|
||||||
|
static const struct mem_controller cpu[] = {
|
||||||
|
#if FIRST_CPU
|
||||||
|
{
|
||||||
|
.node_id = 0,
|
||||||
|
.f0 = PCI_DEV(0, 0x18, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x18, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x18, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x18, 3),
|
||||||
|
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||||
|
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if SECOND_CPU
|
||||||
|
{
|
||||||
|
.node_id = 1,
|
||||||
|
.f0 = PCI_DEV(0, 0x19, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x19, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x19, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x19, 3),
|
||||||
|
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||||
|
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
enable_lapic();
|
||||||
|
init_timer();
|
||||||
|
if (!boot_cpu()) {
|
||||||
|
stop_this_cpu();
|
||||||
|
}
|
||||||
|
pc87360_enable_serial();
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
setup_default_resource_map();
|
||||||
|
setup_coherent_ht_domain();
|
||||||
|
enumerate_ht_chain(0);
|
||||||
|
distinguish_cpu_resets(0);
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
print_pci_devices();
|
||||||
|
#endif
|
||||||
|
enable_smbus();
|
||||||
|
#if 0
|
||||||
|
dump_spd_registers(&cpu[0]);
|
||||||
|
#endif
|
||||||
|
memreset_setup();
|
||||||
|
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
dump_pci_devices();
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
dump_pci_device(PCI_DEV(0, 0x18, 2));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check all of memory */
|
||||||
|
#if 0
|
||||||
|
msr_t msr;
|
||||||
|
msr = rdmsr(TOP_MEM);
|
||||||
|
print_debug("TOP_MEM: ");
|
||||||
|
print_debug_hex32(msr.hi);
|
||||||
|
print_debug_hex32(msr.lo);
|
||||||
|
print_debug("\r\n");
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
ram_check(0x00000000, msr.lo);
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
static const struct {
|
||||||
|
unsigned long lo, hi;
|
||||||
|
} check_addrs[] = {
|
||||||
|
/* Check 16MB of memory @ 0*/
|
||||||
|
{ 0x00000000, 0x01000000 },
|
||||||
|
#if TOTAL_CPUS > 1
|
||||||
|
/* Check 16MB of memory @ 2GB */
|
||||||
|
{ 0x80000000, 0x81000000 },
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
int i;
|
||||||
|
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
|
||||||
|
ram_check(check_addrs[i].lo, check_addrs[i].hi);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
5
src/mainboard/Iwill/DK8X/chip.h
Normal file
5
src/mainboard/Iwill/DK8X/chip.h
Normal file
|
|
@ -0,0 +1,5 @@
|
||||||
|
struct chip_control mainboard_arima_hdama_control;
|
||||||
|
|
||||||
|
struct mainboard_arima_hdama_config {
|
||||||
|
int nothing;
|
||||||
|
};
|
||||||
74
src/mainboard/Iwill/DK8X/cmos.layout
Normal file
74
src/mainboard/Iwill/DK8X/cmos.layout
Normal file
|
|
@ -0,0 +1,74 @@
|
||||||
|
entries
|
||||||
|
|
||||||
|
#start-bit length config config-ID name
|
||||||
|
#0 8 r 0 seconds
|
||||||
|
#8 8 r 0 alarm_seconds
|
||||||
|
#16 8 r 0 minutes
|
||||||
|
#24 8 r 0 alarm_minutes
|
||||||
|
#32 8 r 0 hours
|
||||||
|
#40 8 r 0 alarm_hours
|
||||||
|
#48 8 r 0 day_of_week
|
||||||
|
#56 8 r 0 day_of_month
|
||||||
|
#64 8 r 0 month
|
||||||
|
#72 8 r 0 year
|
||||||
|
#80 4 r 0 rate_select
|
||||||
|
#84 3 r 0 REF_Clock
|
||||||
|
#87 1 r 0 UIP
|
||||||
|
#88 1 r 0 auto_switch_DST
|
||||||
|
#89 1 r 0 24_hour_mode
|
||||||
|
#90 1 r 0 binary_values_enable
|
||||||
|
#91 1 r 0 square-wave_out_enable
|
||||||
|
#92 1 r 0 update_finished_enable
|
||||||
|
#93 1 r 0 alarm_interrupt_enable
|
||||||
|
#94 1 r 0 periodic_interrupt_enable
|
||||||
|
#95 1 r 0 disable_clock_updates
|
||||||
|
#96 288 r 0 temporary_filler
|
||||||
|
0 384 r 0 reserved_memory
|
||||||
|
384 1 e 4 boot_option
|
||||||
|
385 1 e 4 last_boot
|
||||||
|
386 1 e 1 ECC_memory
|
||||||
|
388 4 r 0 reboot_bits
|
||||||
|
392 3 e 5 baud_rate
|
||||||
|
400 1 e 1 power_on_after_fail
|
||||||
|
412 4 e 6 debug_level
|
||||||
|
416 4 e 7 boot_first
|
||||||
|
420 4 e 7 boot_second
|
||||||
|
424 4 e 7 boot_third
|
||||||
|
428 4 h 0 boot_index
|
||||||
|
432 8 h 0 boot_countdown
|
||||||
|
1008 16 h 0 check_sum
|
||||||
|
|
||||||
|
enumerations
|
||||||
|
|
||||||
|
#ID value text
|
||||||
|
1 0 Disable
|
||||||
|
1 1 Enable
|
||||||
|
2 0 Enable
|
||||||
|
2 1 Disable
|
||||||
|
4 0 Fallback
|
||||||
|
4 1 Normal
|
||||||
|
5 0 115200
|
||||||
|
5 1 57600
|
||||||
|
5 2 38400
|
||||||
|
5 3 19200
|
||||||
|
5 4 9600
|
||||||
|
5 5 4800
|
||||||
|
5 6 2400
|
||||||
|
5 7 1200
|
||||||
|
6 6 Notice
|
||||||
|
6 7 Info
|
||||||
|
6 8 Debug
|
||||||
|
6 9 Spew
|
||||||
|
7 0 Network
|
||||||
|
7 1 HDD
|
||||||
|
7 2 Floppy
|
||||||
|
7 8 Fallback_Network
|
||||||
|
7 9 Fallback_HDD
|
||||||
|
7 10 Fallback_Floppy
|
||||||
|
#7 3 ROM
|
||||||
|
|
||||||
|
checksums
|
||||||
|
|
||||||
|
checksum 392 1007 1008
|
||||||
|
|
||||||
|
|
||||||
42
src/mainboard/Iwill/DK8X/failover.c
Normal file
42
src/mainboard/Iwill/DK8X/failover.c
Normal file
|
|
@ -0,0 +1,42 @@
|
||||||
|
#define ASSEMBLY 1
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include "arch/romcc_io.h"
|
||||||
|
#include "pc80/mc146818rtc_early.c"
|
||||||
|
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||||
|
#include "northbridge/amd/amdk8/early_ht.c"
|
||||||
|
#include "cpu/p6/boot_cpu.c"
|
||||||
|
#include "northbridge/amd/amdk8/reset_test.c"
|
||||||
|
|
||||||
|
static void main(void)
|
||||||
|
{
|
||||||
|
/* Nothing special needs to be done to find bus 0 */
|
||||||
|
/* Allow the HT devices to be found */
|
||||||
|
enumerate_ht_chain(0);
|
||||||
|
|
||||||
|
/* Setup the 8111 */
|
||||||
|
amd8111_enable_rom();
|
||||||
|
|
||||||
|
/* Is this a cpu reset? */
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
if (last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
} else {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Is this a deliberate reset by the bios */
|
||||||
|
else if (bios_reset_detected() && last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
/* Is this a secondary cpu? */
|
||||||
|
else if (!boot_cpu() && last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
/* This is the primary cpu how should I boot? */
|
||||||
|
else if (do_normal_boot()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
}
|
||||||
52
src/mainboard/Iwill/DK8X/irq_tables.c
Normal file
52
src/mainboard/Iwill/DK8X/irq_tables.c
Normal file
|
|
@ -0,0 +1,52 @@
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
|
||||||
|
#define IRQ_ROUTER_BUS 1
|
||||||
|
#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
|
||||||
|
#define IRQ_ROUTER_VENDOR 0x1022
|
||||||
|
#define IRQ_ROUTER_DEVICE 0x746b
|
||||||
|
|
||||||
|
#define AVAILABLE_IRQS 0xdef8
|
||||||
|
#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
|
||||||
|
{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
|
||||||
|
{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
|
||||||
|
|
||||||
|
/* Each IRQ_SLOT entry consists of:
|
||||||
|
* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
|
||||||
|
*/
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
|
||||||
|
* devices on the bus */
|
||||||
|
IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
|
||||||
|
IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
|
||||||
|
0x00, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
IRQ_ROUTER_VENDOR, /* Vendor */
|
||||||
|
IRQ_ROUTER_DEVICE, /* Device */
|
||||||
|
0x00, /* Crap (miniport) */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0x00, /* u8 checksum , mod 256 checksum must give
|
||||||
|
* zero, will be corrected later
|
||||||
|
*/
|
||||||
|
{
|
||||||
|
|
||||||
|
/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
|
||||||
|
|
||||||
|
/* PCI Slot 1-6 */
|
||||||
|
IRQ_SLOT (1, 3,1,0, 2,3,4,1 ),
|
||||||
|
IRQ_SLOT (2, 3,2,0, 3,4,1,2 ),
|
||||||
|
IRQ_SLOT (3, 2,1,0, 2,3,4,1 ),
|
||||||
|
IRQ_SLOT (4, 2,2,0, 3,4,1,2 ),
|
||||||
|
IRQ_SLOT (5, 4,5,0, 2,3,4,1 ),
|
||||||
|
IRQ_SLOT (6, 4,4,0, 1,2,3,4 ),
|
||||||
|
|
||||||
|
/* Onboard NICs */
|
||||||
|
IRQ_SLOT (0, 2,3,0, 4,0,0,0 ),
|
||||||
|
IRQ_SLOT (0, 2,4,0, 4,0,0,0 ),
|
||||||
|
|
||||||
|
/* Let Linux know about bus 1 */
|
||||||
|
IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
|
||||||
|
}
|
||||||
|
};
|
||||||
41
src/mainboard/Iwill/DK8X/mainboard.c
Normal file
41
src/mainboard/Iwill/DK8X/mainboard.c
Normal file
|
|
@ -0,0 +1,41 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/chip.h>
|
||||||
|
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
|
||||||
|
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||||
|
{
|
||||||
|
0, 1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct device_operations mainboard_operations = {
|
||||||
|
.read_resources = root_dev_read_resources,
|
||||||
|
.set_resources = root_dev_set_resources,
|
||||||
|
.enable_resources = enable_childrens_resources,
|
||||||
|
.init = 0,
|
||||||
|
.scan_bus = amdk8_scan_root_bus,
|
||||||
|
.enable = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enumerate(struct chip *chip)
|
||||||
|
{
|
||||||
|
struct chip *child;
|
||||||
|
dev_root.ops = &mainboard_operations;
|
||||||
|
chip->dev = &dev_root;
|
||||||
|
chip->bus = 0;
|
||||||
|
for(child = chip->children; child; child = child->next) {
|
||||||
|
child->bus = &dev_root.link[0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
struct chip_control mainboard_arima_hdama_control = {
|
||||||
|
.enumerate = enumerate,
|
||||||
|
.name = "Arima HDAMA mainboard ",
|
||||||
|
};
|
||||||
|
|
||||||
232
src/mainboard/Iwill/DK8X/mptable.c
Normal file
232
src/mainboard/Iwill/DK8X/mptable.c
Normal file
|
|
@ -0,0 +1,232 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/smp/mpspec.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||||
|
{
|
||||||
|
static const char sig[4] = "PCMP";
|
||||||
|
static const char oem[8] = "LNXI ";
|
||||||
|
static const char productid[12] = "HDAMA ";
|
||||||
|
struct mp_config_table *mc;
|
||||||
|
unsigned char bus_num;
|
||||||
|
unsigned char bus_isa;
|
||||||
|
unsigned char bus_8131_1;
|
||||||
|
unsigned char bus_8131_2;
|
||||||
|
unsigned char bus_8111_1;
|
||||||
|
|
||||||
|
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||||
|
memset(mc, 0, sizeof(*mc));
|
||||||
|
|
||||||
|
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||||
|
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||||
|
mc->mpc_spec = 0x04;
|
||||||
|
mc->mpc_checksum = 0; /* not yet computed */
|
||||||
|
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||||
|
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||||
|
mc->mpc_oemptr = 0;
|
||||||
|
mc->mpc_oemsize = 0;
|
||||||
|
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||||
|
mc->mpc_lapic = LAPIC_ADDR;
|
||||||
|
mc->mpe_length = 0;
|
||||||
|
mc->mpe_checksum = 0;
|
||||||
|
mc->reserved = 0;
|
||||||
|
|
||||||
|
smp_write_processors(mc, processor_map);
|
||||||
|
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
|
||||||
|
/* 8111 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_isa++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8111_1 = 4;
|
||||||
|
bus_isa = 5;
|
||||||
|
}
|
||||||
|
/* 8131-1 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_1 = 2;
|
||||||
|
}
|
||||||
|
/* 8131-2 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_2 = 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* define bus and isa numbers */
|
||||||
|
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||||
|
smp_write_bus(mc, bus_num, "PCI ");
|
||||||
|
}
|
||||||
|
smp_write_bus(mc, bus_isa, "ISA ");
|
||||||
|
|
||||||
|
/* IOAPIC handling */
|
||||||
|
|
||||||
|
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
uint32_t base;
|
||||||
|
/* 8131 apic 3 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
|
||||||
|
if (dev) {
|
||||||
|
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||||
|
smp_write_ioapic(mc, 0x03, 0x11, base);
|
||||||
|
}
|
||||||
|
/* 8131 apic 4 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
|
||||||
|
if (dev) {
|
||||||
|
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||||
|
smp_write_ioapic(mc, 0x04, 0x11, base);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ISA backward compatibility interrupts */
|
||||||
|
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, 0x02, 0x00);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x01, 0x02, 0x01);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, 0x02, 0x02);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x03, 0x02, 0x03);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x04, 0x02, 0x04);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x05, 0x02, 0x05);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x06, 0x02, 0x06);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x07, 0x02, 0x07);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x08, 0x02, 0x08);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x09, 0x02, 0x09);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0a, 0x02, 0x0a);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0b, 0x02, 0x0b);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0c, 0x02, 0x0c);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0d, 0x02, 0x0d);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0e, 0x02, 0x0e);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x0f, 0x02, 0x0f);
|
||||||
|
|
||||||
|
/* Standard local interrupt assignments */
|
||||||
|
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||||
|
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||||
|
|
||||||
|
|
||||||
|
/* PCI Slot 1 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|0, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|1, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|2, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (1<<2)|3, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 2 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|0, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|1, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|2, 0x02, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_2, (2<<2)|3, 0x02, 0x11);
|
||||||
|
|
||||||
|
/* PCI Slot 3 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|0, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|1, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|2, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (1<<2)|3, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 4 */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|0, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|1, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|2, 0x02, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (2<<2)|3, 0x02, 0x11);
|
||||||
|
|
||||||
|
/* PCI Slot 5 */
|
||||||
|
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|0, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|1, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|2, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (5<<2)|3, 0x02, 0x10);
|
||||||
|
|
||||||
|
/* PCI Slot 6 */
|
||||||
|
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|0, 0x02, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|1, 0x02, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|2, 0x02, 0x12);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8111_1, (4<<2)|3, 0x02, 0x13);
|
||||||
|
|
||||||
|
/* On board nics */
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (3<<2)|0, 0x02, 0x13);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||||
|
bus_8131_1, (4<<2)|0, 0x02, 0x13);
|
||||||
|
|
||||||
|
/* There is no extension information... */
|
||||||
|
|
||||||
|
/* Compute the checksums */
|
||||||
|
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||||
|
|
||||||
|
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||||
|
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||||
|
mc, smp_next_mpe_entry(mc));
|
||||||
|
return smp_next_mpe_entry(mc);
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||||
|
{
|
||||||
|
void *v;
|
||||||
|
v = smp_write_floating_table(addr);
|
||||||
|
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Add table
Reference in a new issue