mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
this might be close to right.
This commit is contained in:
Ronald G. Minnich
parent
557849b0a0
commit
1fa1ce67a8
1 changed files with 87 additions and 101 deletions
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@ -63,13 +63,21 @@ jmp intel_830_out
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#define SET_RAM_COMMAND(command) \
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movl $REG_DRAMC, %eax ; \
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PCI_READ_CONFIG_DWORD ; \
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andl $0xffffff80, %eax ; \
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andl $0xffffff8f, %eax ; \
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orl $((command)), %eax ; \
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movl %eax, %edx ; \
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movl $REG_DRAMC, %eax ; \
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PCI_WRITE_CONFIG_DWORD
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#define ENABLE_REFRESH()
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// current thinkpads set this to 15.6 uS.
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#define ENABLE_REFRESH() \
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movl $REG_DRAMC, %eax ; \
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PCI_READ_CONFIG_DWORD ; \
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andl $0xfffff88f, %eax ; \
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orl $((RAM_COMMAND_NORMAL_0)), %eax ; \
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movl %eax, %edx ; \
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movl $REG_DRAMC, %eax ; \
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PCI_WRITE_CONFIG_DWORD
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#define REG_PCICMD0 0x04
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#define REG_PCICMD1 0x05
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@ -84,38 +92,15 @@ jmp intel_830_out
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#define REG_SID1 0x2f
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// FROM HERE ON DOWN IT NEEDS TO BE FIXED -- RGM
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#define REG_MCHCFG 0x50
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#define MCHCFG_CLT 0x40 // CLT (Cpu Latency Timer)
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#define MCHCFG_LMFS_MASK 0x10 // local memory frequency mask
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#define MCHCFG_LMFS_133 0x10 // 133Mhz
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#define MCHCFG_LMFS_100 0x00 // 100Mhz
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#define REG_RRBAR 0x48 // IGNORED. LEAVE AT DEFAULT
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#define REG_GCC0 0x50 // sixteen bits
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#define REG_GCC0_VAL 0xa222
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#define REG_GCC1 0x52 // 16 bits
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#define REG_GCC1_VAL 0x800a
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#define REG_FDHC 0x58 // 8 bits
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#define REG_FDHC_VAL 0
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#define MCHCFG_DPCP_MASK 0x08 // dram paging policy mask
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#define MCHCFG_DPCP_0 0x00 // precharge bank at page miss
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#define MCHCFG_DPCP_1 0x08 // precharge all
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#define MCHCFG_SMFS_MASK 0x04 // memory frequency mask
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#define MCHCFG_SMFS_133 0x04 // 133Mhz
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#define MCHCFG_SMFS_100 0x00 // 100Mhz
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#define REG_APCONT 0x51
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#define REG_DRP 0x52
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#define REG_DRAMC 0x7c
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#define REG_DRAMT 0x53
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#define DRAMT_DCT 0x10
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#define DRAMT_HACQS 0x08 // host aperture cycle queue slot
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#define DRAMT_CL_MASK 0x04 // CAS# latency mask
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#define DRAMT_CL_2 0x04 // 2 SCLK
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#define DRAMT_CL_3 0x00 // 3 SCLK
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#define DRAMT_SRCD 0x02 // RAS# latency. 0 = 3 SCLK, 1 = 2 SCLK
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#define DRAMT_SRP 0x01 // RAS# precharge. 0 = 3 SCLK, 1 = 2 SCLK
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#define REG_DRP2 0x54
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#define REG_FDHC 0x58
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#define FDHC_HEN 0x80 // 0 = no hole, 1 = 15-16MB hole enable.
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// thinkpad pam values. 10 11 11 00 30 11 11
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#define REG_PAM0 0x59
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#define REG_PAM1 0x5A
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@ -126,36 +111,49 @@ jmp intel_830_out
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#define REG_PAM6 0x5F
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#define REG_SMRAM 0x70
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#define REG_MISCC 0x72
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#define MISCC_BYPASS 0x2000
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#define MISCC_CPCME 0x0800
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#define MISCC_WPTC_MASK 0x0030
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#define MISCC_WPTC_100 0x0010
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#define MISCC_WPTC_133 0x0020
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// on current thinkpad, one slot full, 0x2 0x4 0x4 0x4
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#define REG_DRB0 0x60
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#define REG_DRB1 0x61
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#define REG_DRB2 0x62
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#define REG_DRB3 0x63
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#define REG_BUFF_SC 0x92
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#define REG_BUFF_SC2 0x94
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#define REG_DRA 0x70 // 16 bits, 0xff11 on my one-ram thinkpad right now (4kb page on pop, top row EMPTY)
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#define REG_DRA_VAL 0xff11
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// default DRT 10 00 02 00 (0x00020010)
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// Idle timer is 8 clocks, CL is 3
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// Ras to cas is 3, ras precharge is 3
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// i.e. as slow as it gets
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#define REG_DRT 0x78 // 32 bits
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#define REG_DRT_VAL 0x00020010
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#define REG_SM_RCOMP 0x98
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// on thinkpad it is 70 41 00 30 (30004170)
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// rev 0, init complete, power mgmt on, all rows allowed active,
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// page close enable, refresh enabled at 15.6, normal operation
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#define REG_DRAMC 0x7c
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#define REG_DRAMC_VAL 0 // initially, none of these should be set initially.
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#define REG_DTC 0x8c // dram throttling
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#define REG_DTC_VAL 0 // thinkpad ignores it
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// SMM sucks. Leave it off.
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#define REG_SMRAM 0x90
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#define REG_SMRAM_VAL 0x2
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// ignore this one.
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//#define REG_ESMRAMC 0x91
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//#define REG_ESMRAMC_VAL 0x
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// the buffer stuff is 1c 01 22 fc (0xfc22011c) on thinkpad
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#define REG_BUFF_SC 0xec // 32 bits
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#define REG_BUFF_SC_VAL 0xfc22011c
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#define REG_SM0 0x9c
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#define REG_SM1 0x9d
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#define REG_SM2 0x9e
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#define REG_SM3 0x9f
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/* default values for config registers */
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ram_set_registers:
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CS_WRITE_BYTE(REG_PCISTS1, 0x20) // new.
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CS_WRITE_BYTE(REG_SVID0, 0x86)
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CS_WRITE_BYTE(REG_SVID1, 0x80) // new
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CS_WRITE_WORD(REG_GCC0, REG_GCC0_VAL)
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CS_WRITE_WORD(REG_GCC1, REG_GCC1_VAL)
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CS_WRITE_BYTE(REG_FDHC, REG_FDHC_VAL)
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CS_WRITE_BYTE(REG_SID0, 0x30)
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CS_WRITE_BYTE(REG_SID1, 0x11) // new
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CS_WRITE_BYTE(REG_PCICMD1, 0x00) // disable SERR#
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CS_WRITE_BYTE(REG_APCONT, 0x00)
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CS_WRITE_BYTE(REG_DRP2, 0x00)
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CS_WRITE_BYTE(REG_FDHC, 0x00)
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CS_WRITE_BYTE(REG_PAM0, 0x00)
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CS_WRITE_BYTE(REG_PAM1, 0x00)
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CS_WRITE_BYTE(REG_PAM2, 0x00)
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@ -163,51 +161,35 @@ ram_set_registers:
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CS_WRITE_BYTE(REG_PAM4, 0x00)
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CS_WRITE_BYTE(REG_PAM5, 0x00)
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CS_WRITE_BYTE(REG_PAM6, 0x00)
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CS_WRITE_BYTE(REG_SMRAM, 0x00)
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CS_WRITE_BYTE(REG_SM0, 0x46)
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CS_WRITE_BYTE(REG_SM1, 0x83)
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CS_WRITE_BYTE(REG_SM2, 0xc4)
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CS_WRITE_BYTE(REG_SM3, 0x00)
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CS_WRITE_BYTE(REG_DRB0, 0x2)
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CS_WRITE_BYTE(REG_DRB1, 0x4)
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CS_WRITE_BYTE(REG_DRB2, 0x4)
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CS_WRITE_BYTE(REG_DRB3, 0x4)
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CS_WRITE_BYTE(REG_DRA, REG_DRA_VAL)
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CS_WRITE_BYTE(REG_DRT, REG_DRT_VAL)
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CS_WRITE_BYTE(REG_DTC, REG_DTC_VAL)
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CS_WRITE_BYTE(REG_DRAMC, REG_DRAMC_VAL)
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CS_WRITE_BYTE(REG_BUFF_SC, REG_BUFF_SC_VAL)
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#if 0
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CS_WRITE_BYTE(REG_SVID0, 0x86)
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CS_WRITE_BYTE(REG_SVID1, 0x80) // new
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CS_WRITE_BYTE(REG_SID0, 0x30)
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CS_WRITE_BYTE(REG_SID1, 0x11) // new
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#endif
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CS_WRITE_BYTE(REG_PCICMD1, 0x00) // disable SERR#
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// CS_WRITE_BYTE(REG_APCONT, 0x00)
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CS_WRITE_BYTE(REG_SMRAM, REG_SMRAM_VAL)
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RET_LABEL(ram_set_registers)
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ram_set_spd_registers:
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// TODO: SPD
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CS_WRITE_BYTE(REG_MCHCFG, 0x44)
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CS_WRITE_BYTE(0x72, 0x28)
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CS_WRITE_BYTE(0x73, 0x20)
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// CS_WRITE_WORD(REG_MISCC, MISCC_BYPASS | MISCC_CPCME | MISCC_WPTC_133)
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// bypass for 133Mhz.
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// write power throttle
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// 400MB/sec - 133Mhz
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// drp
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CS_WRITE_BYTE(REG_DRP, 0x0E) // 256M, SS, DIMM0
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// dramt
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CS_WRITE_BYTE(REG_DRAMT, 0x18)
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// buff_sc
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// CS_WRITE_WORD(REG_BUFF_SC, 0xffdf) // rows 0/1 - 1.7x8 load
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CS_WRITE_BYTE(0x92, 0xae)
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CS_WRITE_BYTE(0x93, 0x3e)
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// CS_WRITE_WORD(REG_BUFF_SC2, 0xfffe) // row 0 - 2.7x8 load
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CS_WRITE_BYTE(0x94, 0xfe)
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CS_WRITE_BYTE(0x95, 0xff)
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// SM_RCOMP
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CS_WRITE_BYTE(0x98, 0x43)
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CS_WRITE_BYTE(0x99, 0x80)
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CS_WRITE_BYTE(0x9a, 0x43)
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CS_WRITE_BYTE(0x9b, 0x80)
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// There is no explicit power-on on this chp ...
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// all the other non-spd setup is done at this point, so I guess this is a no-op.
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RET_LABEL(ram_set_spd_registers)
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ram_enable_1: .string "Ram Enable 1\r\n"
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@ -286,20 +268,24 @@ enable_sdram:
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// Get CAS latency
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// CAS# =2 clk -> 0x2a -> read 0x150
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// CAS# =3 clk -> 0x3a -> read 0x1D0
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movl $REG_DRAMT, %eax
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PCI_READ_CONFIG_BYTE
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andl $0x4, %eax // bit 2 ( 0 = 3clk, 1 = 2ckl )
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// already set, leave this here as a comment.
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// everything runs slow on the thinkpad, it's all cas3
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// movl $REG_DRAMT, %eax
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// PCI_READ_CONFIG_BYTE
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xorl %eax, %eax // puts all zeros into eax, meaning slow
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andl $0x4, %eax // bit 2 ( 0 = 3clk, 1 = 2clk )
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xorl $0x4, %eax // Inverting bit 2
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shll $2, %eax // MA4 = inv(bit 2)
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orl $0x2a, %eax
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shll $3, %eax
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movl (%eax), %ebx // MRS comand to sdram
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// CONSOLE_DEBUG_TX_HEX32(%eax)
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// Normal operation mode
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CONSOLE_DEBUG_TX_STRING($ram_enable_5)
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SET_RAM_COMMAND(RAM_COMMAND_NORMAL_0) // SPD: 12 (refresh rate)
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ENABLE_REFRESH() // also sets normal mode.
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DO_READ($0x0)
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/*
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