mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
UPSTREAM: northbridge/intel/i945: Add space around operators
BUG=None BRANCH=None TEST=None Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Reviewed-on: https://chromium-review.googlesource.com/388288 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Elyes HAOUAS
chrome-bot
parent
526c25da71
commit
1f6cfca478
6 changed files with 44 additions and 44 deletions
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@ -38,7 +38,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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if (!dev)
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return current;
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pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
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pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
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// MMCFG not supported or not enabled.
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if (!(pciexbar_reg & (1 << 0)))
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@ -105,7 +105,7 @@ void dump_mem(unsigned start, unsigned end)
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{
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unsigned i;
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printk(BIOS_DEBUG, "dump_mem:");
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for (i=start;i<end;i++) {
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for (i = start; i < end; i++) {
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if ((i & 0xf)==0) {
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printk(BIOS_DEBUG, "\n%08x:", i);
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}
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@ -752,7 +752,7 @@ static void i945_setup_pci_express_x16(void)
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};
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int i;
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for (i=0; i<ARRAY_SIZE(reglist); i++) {
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for (i = 0; i < ARRAY_SIZE(reglist); i++) {
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reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]);
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reg32 &= 0x0fffffff;
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reg32 |= (2 << 28);
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@ -121,7 +121,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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for (i = 0; i < 2; i++)
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for (j = 0; j < 0x100; j++)
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/* R=j, G=j, B=j. */
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/* R = j, G = j, B = j. */
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write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
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write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
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@ -423,7 +423,7 @@ static void gma_func0_init(struct device *dev)
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mmiobase = (void *)(uintptr_t)dev->resource_list[0].base;
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graphics_base = dev->resource_list[2].base;
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printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
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printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n",
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pci_read_config32(dev, GMADR),
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pci_read_config32(dev, GTTADR)
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);
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@ -224,15 +224,15 @@ static void northbridge_init(struct device *dev)
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switch (pci_read_config32(dev, SKPAD)) {
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case SKPAD_NORMAL_BOOT_MAGIC:
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printk(BIOS_DEBUG, "Normal boot.\n");
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acpi_slp_type=0;
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acpi_slp_type = 0;
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break;
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case SKPAD_ACPI_S3_MAGIC:
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printk(BIOS_DEBUG, "S3 Resume.\n");
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acpi_slp_type=3;
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acpi_slp_type = 3;
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break;
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default:
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printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
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acpi_slp_type=0;
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acpi_slp_type = 0;
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break;
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}
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}
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@ -96,7 +96,7 @@ void sdram_dump_mchbar_registers(void)
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int i;
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printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
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for (i=0; i<0xfff; i+=4) {
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for (i = 0; i < 0xfff; i+=4) {
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if (MCHBAR32(i) == 0)
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continue;
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printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
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@ -359,7 +359,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
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*
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*/
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for (i=0; i<(2 * DIMM_SOCKETS); i++) {
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for (i = 0; i<(2 * DIMM_SOCKETS); i++) {
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int device = get_dimm_spd_address(sysinfo, i);
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u8 reg8;
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@ -443,7 +443,7 @@ static void sdram_verify_package_type(struct sys_info * sysinfo)
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/* Assume no stacked DIMMs are available until we find one */
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sysinfo->package = 0;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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@ -463,7 +463,7 @@ static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
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SPD_CAS_LATENCY_DDR2_4 |
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SPD_CAS_LATENCY_DDR2_5;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
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cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i),
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SPD_ACCEPTABLE_CAS_LATENCIES);
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@ -519,7 +519,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
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int freq_cas_mask = cas_mask;
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PRINTK_DEBUG("Probing Speed %d\n", j);
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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int device = get_dimm_spd_address(sysinfo, i);
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int current_cas_mask;
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@ -616,7 +616,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
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tRAS_cycles = 4; /* 4 clocks minimum */
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tRAS_time = tRAS_cycles * freq_multiplier;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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u8 reg8;
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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@ -656,7 +656,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
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tRP_cycles = 2; /* 2 clocks minimum */
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tRP_time = tRP_cycles * freq_multiplier;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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u8 reg8;
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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@ -697,7 +697,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
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tRCD_cycles = 2; /* 2 clocks minimum */
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tRCD_time = tRCD_cycles * freq_multiplier;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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u8 reg8;
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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@ -737,7 +737,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
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tWR_cycles = 2; /* 2 clocks minimum */
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tWR_time = tWR_cycles * freq_multiplier;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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u8 reg8;
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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@ -772,7 +772,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
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25, 35, 43 /* DDR2-667 */
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};
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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u8 reg8;
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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@ -818,7 +818,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
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sysinfo->refresh = 0;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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int refresh;
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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@ -849,7 +849,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
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{
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int i;
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for (i=0; i<2*DIMM_SOCKETS; i++) {
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for (i = 0; i < 2*DIMM_SOCKETS; i++) {
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if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
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continue;
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@ -861,7 +861,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo)
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static void sdram_program_dram_width(struct sys_info * sysinfo)
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{
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u16 c0dramw=0, c1dramw=0;
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u16 c0dramw = 0, c1dramw = 0;
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int idx;
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if (sysinfo->dual_channel)
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@ -899,7 +899,7 @@ static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
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{
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int i;
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for (i=0; i<16; i++)
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for (i = 0; i < 16; i++)
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MCHBAR32(offset+(i*4)) = slew_rate_table[i];
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}
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@ -1242,12 +1242,12 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
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/* We drive both channels with the same speed */
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switch (sysinfo->memory_frequency) {
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case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
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case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
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case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
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case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */
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case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */
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case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */
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}
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for (i=0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
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MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
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MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
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@ -1559,10 +1559,10 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
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static int sdram_set_row_attributes(struct sys_info *sysinfo)
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{
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int i, value;
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u16 dra0=0, dra1=0, dra = 0;
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u16 dra0 = 0, dra1 = 0, dra = 0;
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printk(BIOS_DEBUG, "Setting row attributes...\n");
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for (i=0; i < 2 * DIMM_SOCKETS; i++) {
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for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
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u16 device;
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u8 columnsrows;
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@ -1616,7 +1616,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo)
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MCHBAR16(C0BNKARC) &= 0xff00;
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off32 = C0BNKARC;
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for (i=0; i < 2 * DIMM_SOCKETS; i++) {
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for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
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/* Switch to second channel */
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if (i == DIMM_SOCKETS)
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off32 = C1BNKARC;
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@ -1662,7 +1662,7 @@ static void sdram_program_cke_tristate(struct sys_info *sysinfo)
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reg32 = MCHBAR32(C0DRC1);
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for (i=0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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if (sysinfo->banksize[i] == 0) {
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reg32 |= (1 << (16 + i));
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}
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@ -1676,7 +1676,7 @@ static void sdram_program_cke_tristate(struct sys_info *sysinfo)
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/* Do we have to do this if we're in Single Channel Mode? */
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reg32 = MCHBAR32(C1DRC1);
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for (i=4; i < 8; i++) {
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for (i = 4; i < 8; i++) {
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if (sysinfo->banksize[i] == 0) {
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reg32 |= (1 << (12 + i));
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}
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@ -1695,7 +1695,7 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo)
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reg32 = MCHBAR32(C0DRC2);
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for (i=0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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if (sysinfo->banksize[i] == 0) {
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reg32 |= (1 << (24 + i));
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}
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@ -1704,7 +1704,7 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo)
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reg32 = MCHBAR32(C1DRC2);
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for (i=4; i < 8; i++) {
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for (i = 4; i < 8; i++) {
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if (sysinfo->banksize[i] == 0) {
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reg32 |= (1 << (20 + i));
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}
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@ -1832,7 +1832,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
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/* Determine page size */
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reg32 = 0;
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page_size = 1; /* Default: 1k pagesize */
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for (i=0; i< 2*DIMM_SOCKETS; i++) {
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for (i = 0; i< 2*DIMM_SOCKETS; i++) {
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if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
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sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
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page_size = 2; /* 2k pagesize */
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@ -1932,7 +1932,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
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MCHBAR32(DCC) = reg32;
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PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
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PRINTK_DEBUG("DCC = 0x%08x\n", MCHBAR32(DCC));
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}
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static void sdram_program_pll_settings(struct sys_info *sysinfo)
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@ -1980,7 +1980,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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voltage = VOLTAGE_1_05;
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if (MCHBAR32(DFT_STRAP1) & (1 << 20))
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voltage = VOLTAGE_1_50;
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printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
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printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05)?"1.05V":"1.5V");
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/* Gate graphics hardware for frequency change */
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reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
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@ -2006,7 +2006,7 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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if (freq != CRCLK_400MHz) {
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/* What chipset are we? Force 166MHz for GMS */
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
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if (reg8==2)
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if (reg8 == 2)
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freq = CRCLK_166MHz;
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}
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@ -2043,9 +2043,9 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
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}
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if (second_vco) {
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sysinfo->clkcfg_bit7=1;
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sysinfo->clkcfg_bit7 = 1;
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} else {
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sysinfo->clkcfg_bit7=0;
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sysinfo->clkcfg_bit7 = 0;
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}
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/* Graphics Core Render Clock */
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@ -2089,7 +2089,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
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clkcfg = MCHBAR32(CLKCFG);
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printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
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printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", clkcfg);
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clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
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@ -2153,7 +2153,7 @@ cache_code:
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goto vco_update;
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out:
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printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
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printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", MCHBAR32(CLKCFG));
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printk(BIOS_DEBUG, "ok\n");
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}
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@ -2504,7 +2504,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
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MCHBAR32(UPMC3) = 0x000f06ff;
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for (i=0; i<5; i++) {
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for (i = 0; i < 5; i++) {
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MCHBAR32(UPMC3) &= ~(1 << 16);
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MCHBAR32(UPMC3) |= (1 << 16);
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}
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@ -2685,7 +2685,7 @@ static void sdram_save_receive_enable(void)
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* so we grab bytes 128 - 131 to save the receive enable values
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*/
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for (i=0; i<4; i++)
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for (i = 0; i < 4; i++)
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cmos_write(values[i], 128 + i);
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}
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@ -2695,7 +2695,7 @@ static void sdram_recover_receive_enable(void)
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u32 reg32;
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u8 values[4];
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||||
for (i=0; i<4; i++)
|
||||
for (i = 0; i < 4; i++)
|
||||
values[i] = cmos_read(128 + i);
|
||||
|
||||
MCHBAR8(C0WL0REOST) = values[0];
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue