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Change v3 makefile rules to be source-based, part I.

Browse source 
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.

This pepares the way for additional optimizations during compile and
link time.

Build tested and boot tested on Qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-08-18 11:15:43 +00:00
parent 7102949d76
commit 1b22622323
18 changed files with 52 additions and 49 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

35
arch/x86/Makefile
View file

@ -3,6 +3,7 @@
## ##
## Copyright (C) 2006-2007 coresystems GmbH ## Copyright (C) 2006-2007 coresystems GmbH
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH) ## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
## Copyright (C) 2007-2008 Carl-Daniel Hailfinger
## ##
## This program is free software; you can redistribute it and/or modify ## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by ## it under the terms of the GNU General Public License as published by
@ -98,15 +99,15 @@ $(obj)/coreboot.bootblock: $(obj)/coreboot.vpd $(obj)/stage0.init
# #
STAGE0_LIB_OBJ = uart8250.o mem.o lar.o delay.o vtxprintf.o \ STAGE0_LIB_SRC = uart8250.c mem.c lar.c delay.c vtxprintf.c \
vsprintf.o console.o string.o $(DECOMPRESSORS) vsprintf.c console.c string.c $(DECOMPRESSORS)
STAGE0_ARCH_X86_OBJ = stage1.o serial.o speaker.o \ STAGE0_ARCH_X86_SRC = stage1.c serial.c speaker.c \
udelay_io.o mc146818rtc.o post_code.o \ udelay_io.c mc146818rtc.c post_code.c \
pci_ops_conf1.o resourcemap.o pci_ops_conf1.c resourcemap.c
ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y) ifeq ($(CONFIG_PAYLOAD_ELF_LOADER),y)
STAGE0_LIB_OBJ += elfboot.o STAGE0_LIB_SRC += elfboot.c
STAGE0_ARCH_X86_OBJ += archelfboot.o STAGE0_ARCH_X86_SRC += archelfboot.c
endif endif
ifeq ($(CONFIG_CPU_I586),y) ifeq ($(CONFIG_CPU_I586),y)
@ -114,12 +115,12 @@ ifeq ($(CONFIG_CPU_I586),y)
else else
ifeq ($(CONFIG_CPU_AMD_GEODELX),y) ifeq ($(CONFIG_CPU_AMD_GEODELX),y)
STAGE0_CAR_OBJ = geodelx/stage0.o STAGE0_CAR_OBJ = geodelx/stage0.o
STAGE0_ARCH_X86_OBJ += geodelx/stage1.o STAGE0_ARCH_X86_SRC += geodelx/stage1.c
STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o STAGE0_ARCH_X86_SRC += ../../northbridge/amd/geodelx/geodelxinit.c
else else
ifeq ($(CONFIG_CPU_AMD_K8),y) ifeq ($(CONFIG_CPU_AMD_K8),y)
STAGE0_CAR_OBJ = amd/stage0.o STAGE0_CAR_OBJ = amd/stage0.o
STAGE0_ARCH_X86_OBJ += amd/k8/stage1.o STAGE0_ARCH_X86_SRC += amd/k8/stage1.c
endif endif
endif endif
endif endif
@ -130,10 +131,12 @@ else
PARSEELF = -e PARSEELF = -e
endif endif
STAGE0_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE0_LIB_OBJ)) \ STAGE0_SRC := $(patsubst %,$(src)/lib/%,$(STAGE0_LIB_SRC)) \
$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_ARCH_X86_OBJ)) \ $(patsubst %,$(src)/arch/x86/%,$(STAGE0_ARCH_X86_SRC)) \
$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \ $(STAGE0_MAINBOARD_SRC) $(STAGE0_CHIPSET_SRC)
$(STAGE0_MAINBOARD_OBJ) $(STAGE0_CHIPSET_OBJ)
STAGE0_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE0_SRC)) \
$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ))
$(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ) $(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
$(Q)# We need to be careful. If stage0.o gets bigger than $(Q)# We need to be careful. If stage0.o gets bigger than
@ -182,7 +185,7 @@ ifeq ($(CONFIG_PIRQ_TABLE),y)
STAGE2_ARCH_X86_SRC += pirq_routing.c STAGE2_ARCH_X86_SRC += pirq_routing.c
endif endif
STAGE2_DYNAMIC_OBJ = statictree.o STAGE2_DYNAMIC_SRC = $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c
STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \ STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
$(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \ $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
@ -195,7 +198,7 @@ STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
# This one is special because the static tree object ends up in the mainboard # This one is special because the static tree object ends up in the mainboard
# dir of the object tree. # dir of the object tree.
STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ)) STAGE2_OBJ += $(patsubst $(obj)/%.c,$(obj)/%.o,$(STAGE2_DYNAMIC_SRC))
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)

4
lib/Makefile
View file

@ -21,10 +21,10 @@
DECOMPRESSORS := DECOMPRESSORS :=
ifeq ($(CONFIG_COMPRESSION_LZMA),y) ifeq ($(CONFIG_COMPRESSION_LZMA),y)
DECOMPRESSORS += lzma.o DECOMPRESSORS += lzma.c
endif endif
ifeq ($(CONFIG_COMPRESSION_NRV2B),y) ifeq ($(CONFIG_COMPRESSION_NRV2B),y)
DECOMPRESSORS += nrv2b.o DECOMPRESSORS += nrv2b.c
endif endif
# #

2
mainboard/adl/msm800sev/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

2
mainboard/amd/db800/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

2
mainboard/amd/norwich/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

16
mainboard/amd/serengeti/Makefile
View file

@ -19,14 +19,14 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
$(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
$(obj)/southbridge/amd/amd8111/stage1_smbus.o \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \
$(obj)/southbridge/amd/amd8111/stage1_ctrl.o \ $(src)/southbridge/amd/amd8111/stage1_ctrl.c \
$(obj)/northbridge/amd/k8/coherent_ht.o \ $(src)/northbridge/amd/k8/coherent_ht.c \
$(obj)/northbridge/amd/k8/incoherent_ht.o \ $(src)/northbridge/amd/k8/incoherent_ht.c \
$(obj)/northbridge/amd/k8/libstage1.o \ $(src)/northbridge/amd/k8/libstage1.c \
$(obj)/lib/clog2.o $(src)/lib/clog2.c
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \ $(src)/northbridge/amd/k8/raminit.c \

2
mainboard/artecgroup/dbe61/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

2
mainboard/artecgroup/dbe62/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

2
mainboard/emulation/qemu-x86/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
# #
# This is going to be the init RAM code. # This is going to be the init RAM code.

12
mainboard/gigabyte/m57sli/Makefile
View file

@ -19,12 +19,12 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
$(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
$(obj)/southbridge/nvidia/mcp55/stage1_smbus.o \ $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
$(obj)/northbridge/amd/k8/coherent_ht.o \ $(src)/northbridge/amd/k8/coherent_ht.c \
$(obj)/northbridge/amd/k8/incoherent_ht.o \ $(src)/northbridge/amd/k8/incoherent_ht.c \
$(obj)/lib/clog2.o $(src)/lib/clog2.c
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \ $(src)/northbridge/amd/k8/raminit.c \

2
mainboard/pcengines/alix1c/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

2
mainboard/pcengines/alix2c3/Makefile
View file

@ -19,7 +19,7 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
## ##
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \

2
southbridge/amd/amd8111/Makefile
View file

@ -34,7 +34,7 @@ STAGE2_CHIPSET_SRC += \
$(src)/southbridge/amd/amd8111/usb.c \ $(src)/southbridge/amd/amd8111/usb.c \
$(src)/southbridge/amd/amd8111/usb2.c $(src)/southbridge/amd/amd8111/usb2.c
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/amd8111/stage1.o STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/amd8111/stage1.c
endif endif

2
southbridge/amd/cs5536/Makefile
View file

@ -27,6 +27,6 @@ ifeq ($(CONFIG_PIRQ_TABLE),y)
STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c
endif endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/stage1.c
endif endif

2
southbridge/nvidia/mcp55/Makefile
View file

@ -36,7 +36,7 @@ STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/ide.c \
$(src)/southbridge/nvidia/mcp55/usb.c \ $(src)/southbridge/nvidia/mcp55/usb.c \
$(src)/southbridge/nvidia/mcp55/usb2.c $(src)/southbridge/nvidia/mcp55/usb2.c
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o STAGE0_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/stage1.c
endif endif

4
superio/fintek/f71805f/Makefile
View file

@ -20,8 +20,8 @@
ifeq ($(CONFIG_SUPERIO_FINTEK_F71805F),y) ifeq ($(CONFIG_SUPERIO_FINTEK_F71805F),y)
STAGE0_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/stage1.o STAGE0_CHIPSET_SRC += $(src)/superio/fintek/f71805f/stage1.c
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
# Always add to variables, as there could be more than one Super I/O. # Always add to variables, as there could be more than one Super I/O.
STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c

4
superio/ite/it8716f/Makefile
View file

@ -20,8 +20,8 @@
ifeq ($(CONFIG_SUPERIO_ITE_IT8716F),y) ifeq ($(CONFIG_SUPERIO_ITE_IT8716F),y)
STAGE0_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/stage1.o STAGE0_CHIPSET_SRC += $(src)/superio/ite/it8716f/stage1.c
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
# Always add to variables, as there could be more than one Super I/O. # Always add to variables, as there could be more than one Super I/O.
STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c

4
superio/winbond/w83627hf/Makefile
View file

@ -21,8 +21,8 @@
ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y) ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y)
STAGE0_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/stage1.o STAGE0_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/stage1.c
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
# Always add to variables, as there could be more than one Super I/O. # Always add to variables, as there could be more than one Super I/O.
STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c