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UPSTREAM: mainboard/google/{poppy,soraka}: Disable unused GSPI1 interface

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TEST=Verified that board still boots to OS without any error.

Change-Id: I44c002e71e85017599a3f474941ced51c79e44d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 296c79c9be
Original-Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/20143
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539209
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-06-09 18:41:39 -07:00 • committed by chrome-bot
parent 7fde2e025d
commit 1a1b413abb
3 changed files with 12 additions and 12 deletions
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4
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -182,7 +182,7 @@ chip soc/intel/skylake
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
@ -436,7 +436,7 @@ chip soc/intel/skylake
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard

16
src/mainboard/google/poppy/variants/baseboard/gpio.c
View file

@ -111,14 +111,14 @@ static const struct pad_config gpio_table[] = {
/* B18 : GSPI0_MOSI ==> NC */
PAD_CFG_NC(GPP_B18),
#endif
/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS_L */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* B21 : GSPI1_MISO ==> PCH_SPI_FP_MISO */
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B22 : GSPI1_MOSI ==> PCH_SPI_FP_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
/* B19 : GSPI1_CS# ==> NC */
PAD_CFG_NC(GPP_B19),
/* B20 : GSPI1_CLK ==> NC */
PAD_CFG_NC(GPP_B20),
/* B21 : GSPI1_MISO ==> NC */
PAD_CFG_NC(GPP_B21),
/* B22 : GSPI1_MOSI ==> NC */
PAD_CFG_NC(GPP_B22),
/* B23 : SM1ALERT# ==> NC */
PAD_CFG_NC(GPP_B23),

4
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -182,7 +182,7 @@ chip soc/intel/skylake
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
@ -424,7 +424,7 @@ chip soc/intel/skylake
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 on end # SDCard