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Convert stage2 and initram makefile rules from object to source files.

Browse source 
This creates a clearer distinction between source files in the source 
tree we want to have compiled and indirectly created object/source files 
in the object tree.

It also will make enable us to move to whole-program 
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as 
well.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-08-02 20:56:11 +00:00
parent 41242a63c3
commit 1a09707fd6
20 changed files with 54 additions and 49 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

35
arch/x86/Makefile
View file

@ -178,26 +178,31 @@ $(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
# TODO: This should be compressed with the default compressor. # TODO: This should be compressed with the default compressor.
# #
STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \ STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \
compute_ip_checksum.o string.o compute_ip_checksum.c string.c
STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
ifeq ($(CONFIG_PIRQ_TABLE),y) ifeq ($(CONFIG_PIRQ_TABLE),y)
STAGE2_ARCH_X86_OBJ += pirq_routing.o STAGE2_ARCH_X86_SRC += pirq_routing.c
endif endif
STAGE2_DYNAMIC_OBJ = statictree.o STAGE2_DYNAMIC_OBJ = statictree.o
STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \ STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
$(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \ $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
$(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \ $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
$(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \ $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
$(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ) STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
# This one is special because the static tree object ends up in the mainboard
# dir of the object tree.
STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
@ -214,7 +219,7 @@ endif
STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ)) STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
$(Q)# leave a .o with full symbols in it for debugging. $(Q)# leave a .o with full symbols in it for debugging.
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \ $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@ -260,9 +265,9 @@ $(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S
$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@ $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ) $(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
$(Q)# initram links against stage0 $(Q)# initram links against stage0
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \

4
device/Makefile
View file

@ -24,6 +24,6 @@ $(obj)/device/%.o: $(src)/device/%.c
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(INITCFLAGS) -c $< -o $@ $(Q)$(CC) $(INITCFLAGS) -c $< -o $@
STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \ STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c

4
mainboard/adl/msm800sev/Makefile
View file

@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/amd/db800/Makefile
View file

@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/amd/norwich/Makefile
View file

@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/artecgroup/dbe61/Makefile
View file

@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/artecgroup/dbe62/Makefile
View file

@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c $(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/emulation/qemu-x86/Makefile
View file

@ -28,10 +28,10 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
# directory and is built from what was auto.c in v2. # directory and is built from what was auto.c in v2.
# #
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c $(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
STAGE2_MAINBOARD_OBJ = vga.o STAGE2_MAINBOARD_SRC = vga.c
# #
# VPD or SIP ROM or... how does NVIDIA call it? # VPD or SIP ROM or... how does NVIDIA call it?

4
mainboard/gigabyte/m57sli/Makefile
View file

@ -21,9 +21,9 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/pcengines/alix1c/Makefile
View file

@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

4
mainboard/pcengines/alix2c3/Makefile
View file

@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \ $(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c $(src)/arch/x86/geodelx/geodelx.c
STAGE2_MAINBOARD_OBJ = STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd: $(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n" $(Q)printf " BUILD DUMMY VPD\n"

8
northbridge/amd/geodelx/Makefile
View file

@ -21,9 +21,9 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
$(obj)/northbridge/amd/geodelx/vsmsetup.o \ $(src)/northbridge/amd/geodelx/vsmsetup.c \
$(obj)/util/x86emu/vm86_gdt.o \ $(src)/util/x86emu/vm86_gdt.c \
$(obj)/northbridge/amd/geodelx/grphinit.o $(src)/northbridge/amd/geodelx/grphinit.c
endif endif

2
northbridge/amd/k8/Makefile
View file

@ -21,6 +21,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y) ifeq ($(CONFIG_NORTHBRIDGE_AMD_K8),y)
STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/k8/raminit.o STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/raminit.c
endif endif

2
northbridge/intel/i440bxemulation/Makefile
View file

@ -21,6 +21,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y) ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
endif endif

4
southbridge/amd/cs5536/Makefile
View file

@ -21,10 +21,10 @@
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
ifeq ($(CONFIG_PIRQ_TABLE),y) ifeq ($(CONFIG_PIRQ_TABLE),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/irq_tables.c
endif endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o

2
southbridge/intel/i82371eb/Makefile
View file

@ -20,6 +20,6 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
endif endif

4
southbridge/nvidia/mcp55/Makefile
View file

@ -21,10 +21,10 @@
ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y) ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/mcp55.o STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/mcp55.c
ifeq ($(CONFIG_PIRQ_TABLE),y) ifeq ($(CONFIG_PIRQ_TABLE),y)
STAGE2_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/irq_tables.o STAGE2_CHIPSET_SRC += $(src)/southbridge/nvidia/mcp55/irq_tables.c
endif endif
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o STAGE0_CHIPSET_OBJ += $(obj)/southbridge/nvidia/mcp55/stage1.o

2
superio/fintek/f71805f/Makefile
View file

@ -24,6 +24,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/stage1.o
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O. # Always add to variables, as there could be more than one Super I/O.
STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
endif endif

2
superio/ite/it8716f/Makefile
View file

@ -24,6 +24,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/stage1.o
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O. # Always add to variables, as there could be more than one Super I/O.
STAGE2_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/superio.o STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c
endif endif

2
superio/winbond/w83627hf/Makefile
View file

@ -25,6 +25,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/stage1.o
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O. # Always add to variables, as there could be more than one Super I/O.
STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
endif endif