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https://github.com/fail0verflow/switch-coreboot.git
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cvs ug.
This commit is contained in:
Ronald G. Minnich
parent
bd2c5afc45
commit
196ed499c1
1 changed files with 234 additions and 0 deletions
234
romimages/RON_L440GX/Makefile
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234
romimages/RON_L440GX/Makefile
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CPUFLAGS=-DL440GX -Di686 -Di586 -DINTEL_BRIDGE_CONFIG -DPIIX4E_NVRAM
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CPUFLAGS += -D__KERNEL__
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CPUFLAGS += -DINTEL_PPRO_MTRR -DPIIX4E_KEYBOARD
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CPUFLAGS += -DSMP
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#CPUFLAGS += -DHAVE_FRAMEBUFFER
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DZKERNEL_START=0xfff40000
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CPUFLAGS += -DZKERNEL_MASK=0x3ed
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 debug 3 single"'
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CPUFLAGS += -DPIIX4_DEVFN=0x90
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CPUFLAGS += -DUPDATE_MICROCODE
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CPUFLAGS += -DCONFIGURE_L2_CACHE
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LINUX=$(TOP)/../linux-2.4.0-test6.l440gx
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include
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CFLAGS=$(INCLUDES) -O2 $(CPUFLAGS) -Ilinux/include -Wall
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OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o
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OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
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OBJECTS += southbridge.o northbridge.o
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#OBJECTS += pci.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += cpuid.o
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OBJECTS += serial_subr.o
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OBJECTS += mpspec.o
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OBJECTS += microcode.o
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OBJECTS += keyboard.o
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OBJECTS += l2_cache.o
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LINK = ld -T $(TOP)/src/mainboard/intel/l440gx/ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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cp romimage /tmp
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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# crt0 actually includes .inc files.
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# For self-documenting purposes, we put the FULL PATH of the
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# .inc files (relative to $TOP/src) in crt0.S.
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# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
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# To make this work, add the extra -I $(TOP)/src here.
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crt0.s: $(TOP)/src/mainboard/intel/l440gx/crt0.S
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$(CCASM) -I $(TOP)/src -E $< > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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mainboard.o: $(TOP)/src/mainboard/intel/l440gx/mainboard.c
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cc $(CFLAGS) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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southbridge.o: $(TOP)/src/southbridge/intel/piix4e/southbridge.c
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cc $(CFLAGS) -c $<
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northbridge.o: $(TOP)/src/northbridge/intel/440gx/northbridge.c
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cc $(CFLAGS) -c $<
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#superio.o: $(TOP)/src/superio/intel/950/superio.c
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# cc $(CFLAGS) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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l2_cache.o: $(TOP)/src/cpu/p6/l2_cache.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=640k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: $(LINUX)/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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rm -f docipl
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# here begins stupid stuff for the phlash program. It's ugly.
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#PHLASH_BASE_NAME=p11-0105
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PHLASH_BASE_NAME=p11-0102
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#PHLASH_BASE_NAME=p12-0115
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#PHLASH_BASE_NAME=p13-0125
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phlash: vmlinux.bin.gz linuxbios.rom headers
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rm -f xa?
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split -b 64k vmlinux.bin.gz
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# Now just touch them if we have a really
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# small kernel!
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touch xaa xab xac xad xae xaf xag xah
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# this if starting at bank 4, and proceeding on. Unused banks are dups
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# intel nvram is odd all of the banks are byte swapped
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cat $(PHLASH_BASE_NAME).bi1.header xaa > $(PHLASH_BASE_NAME).bi1
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cat $(PHLASH_BASE_NAME).bi3.header xab > $(PHLASH_BASE_NAME).bi3
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cat $(PHLASH_BASE_NAME).bi2.header xac > $(PHLASH_BASE_NAME).bi2
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cat $(PHLASH_BASE_NAME).bi4.header xad > $(PHLASH_BASE_NAME).bi4
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cat $(PHLASH_BASE_NAME).bi7.header xae > $(PHLASH_BASE_NAME).bi7
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cat $(PHLASH_BASE_NAME).bi6.header xaf > $(PHLASH_BASE_NAME).bi6
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cat $(PHLASH_BASE_NAME).bi9.header xag > $(PHLASH_BASE_NAME).bi9
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cat $(PHLASH_BASE_NAME).bi8.header xah > $(PHLASH_BASE_NAME).bi8
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cat $(PHLASH_BASE_NAME).bia.header linuxbios.rom > $(PHLASH_BASE_NAME).bia
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# Part o & 5 seem not to be written reliably for some reason...
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cat $(PHLASH_BASE_NAME).bio.header /dev/null > $(PHLASH_BASE_NAME).bio
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cat $(PHLASH_BASE_NAME).bi5.header /dev/null > $(PHLASH_BASE_NAME).bi5
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sh -x $(TOP)/src/mainboard/intel/l440gx/BUILD_PHLASH_FILES $(PHLASH_BASE_NAME)
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headers: \
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$(PHLASH_BASE_NAME).bi1.header \
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$(PHLASH_BASE_NAME).bi2.header \
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$(PHLASH_BASE_NAME).bi3.header \
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$(PHLASH_BASE_NAME).bi4.header \
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$(PHLASH_BASE_NAME).bi5.header \
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$(PHLASH_BASE_NAME).bi6.header \
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$(PHLASH_BASE_NAME).bi7.header \
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$(PHLASH_BASE_NAME).bi8.header \
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$(PHLASH_BASE_NAME).bi9.header \
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$(PHLASH_BASE_NAME).bia.header \
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$(PHLASH_BASE_NAME).bio.header
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# This builds the headers from the intel flash disk.
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# we are not distributing this disk; you need to get it.
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BUILDHEADER=dd if=$< of=$@ bs=1 count=160
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$(PHLASH_BASE_NAME).bi1.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi1
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi2.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi2
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi3.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi3
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi4.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi4
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi5.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi5
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi6.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi6
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi7.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi7
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi8.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi8
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bi9.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bi9
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bia.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bia
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$(BUILDHEADER)
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$(PHLASH_BASE_NAME).bio.header: $(TOP)/../intel_flash_disk/$(PHLASH_BASE_NAME).bio
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$(BUILDHEADER)
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