baytrail: initialize punit

The punit is responsible for a number of things. Without
performing the sequence included it won't change processor
frequency when requested and apparently there are some bizarre
hangs introduced if this sequence isn't included either. Lastly,
this needs to come after microcode has been loaded. As that is
done in bootblock the ordering is correct.

One other side effect is that this fixes the graphics devices'
device id. Before it was showing up as the same device id of the
SoC transaction router.

BUG=chrome-os-partner:22880
BUG=chrome-os-partner:23085
BUG=chrome-os-partner:22876
BRANCH=None
TEST=Built and booted.

Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171862
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/baytrail/baytrail/romstage.h

@@ -48,6 +48,7 @@ void asmlinkage romstage_after_car(void);
 void raminit(struct mrc_params *mp, int prev_sleep_state);
 void gfx_init(void);
 void tco_disable(void);
+void punit_init(void);
 
 #if CONFIG_ENABLE_BUILTIN_COM1
 void byt_config_com1_and_enable(void);

src/soc/intel/baytrail/romstage/pmc.c

@@ -33,3 +33,23 @@ void tco_disable(void)
 	reg |= TCO_TMR_HALT;
 	outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
 }
+
+/* This sequence signals the PUNIT to start running. */
+void punit_init(void)
+{
+	uint32_t reg;
+
+	/* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */
+	reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE;
+	pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
+	reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) |
+	     IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2;
+	pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
+
+	/* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */
+	reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE;
+	pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
+	reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) |
+	     IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0;
+	pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
+}

src/soc/intel/baytrail/romstage/romstage.c

@@ -126,6 +126,8 @@ void romstage_common(struct romstage_params *params)
 
 	console_init();
 
+	punit_init();
+
 	gfx_init();
 
 	mark_ts(params, timestamp_get());