From 17d2e172cabc1d51b4402718201198550b380a46 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Thu, 14 Aug 2008 09:37:46 +0000 Subject: [PATCH] Use the correct MCP55 PCI subsystem ID setting function. This fixes a genuine bug in the MCP55 code. Moving this away from PCI ops is the next goal. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Ronald G. Minnich git-svn-id: svn://coreboot.org/repository/coreboot-v3@762 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- southbridge/nvidia/mcp55/ide.c | 8 +------- southbridge/nvidia/mcp55/lpc.c | 23 ++++++++--------------- southbridge/nvidia/mcp55/mcp55.c | 12 ++++++++++++ southbridge/nvidia/mcp55/mcp55.h | 4 ++++ southbridge/nvidia/mcp55/pci.c | 2 +- southbridge/nvidia/mcp55/pcie.c | 10 +++++----- southbridge/nvidia/mcp55/sata.c | 9 +-------- southbridge/nvidia/mcp55/smbus.c | 15 +++++---------- southbridge/nvidia/mcp55/usb.c | 7 +------ southbridge/nvidia/mcp55/usb2.c | 7 +------ 10 files changed, 39 insertions(+), 58 deletions(-) diff --git a/southbridge/nvidia/mcp55/ide.c b/southbridge/nvidia/mcp55/ide.c index 2c8685ed7c..90cf85846f 100644 --- a/southbridge/nvidia/mcp55/ide.c +++ b/southbridge/nvidia/mcp55/ide.c @@ -68,12 +68,6 @@ static void ide_init(struct device *dev) #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif - -#warning set subsystem id on mcp55 ide -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_ide = { @@ -86,6 +80,6 @@ struct device_operations mcp55_ide = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; diff --git a/southbridge/nvidia/mcp55/lpc.c b/southbridge/nvidia/mcp55/lpc.c index 96994475e1..5277550beb 100644 --- a/southbridge/nvidia/mcp55/lpc.c +++ b/southbridge/nvidia/mcp55/lpc.c @@ -338,13 +338,6 @@ static void mcp55_lpc_enable_resources(struct device *dev) mcp55_lpc_enable_childrens_resources(dev); } -/* This is awaiting the subsystem support in dtc/dts -static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -*/ struct device_operations mcp55_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, @@ -355,7 +348,7 @@ struct device_operations mcp55_lpc = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pro = { @@ -368,7 +361,7 @@ struct device_operations mcp55_pro = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc2 = { @@ -381,7 +374,7 @@ struct device_operations mcp55_lpc2 = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc3 = { @@ -394,7 +387,7 @@ struct device_operations mcp55_lpc3 = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc4 = { @@ -407,7 +400,7 @@ struct device_operations mcp55_lpc4 = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc5 = { @@ -420,7 +413,7 @@ struct device_operations mcp55_lpc5 = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc6 = { @@ -433,7 +426,7 @@ struct device_operations mcp55_lpc6 = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpcslave = { @@ -446,5 +439,5 @@ struct device_operations mcp55_lpcslave = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = lpc_slave_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; diff --git a/southbridge/nvidia/mcp55/mcp55.c b/southbridge/nvidia/mcp55/mcp55.c index 6dc472370e..ed679f5bcb 100644 --- a/southbridge/nvidia/mcp55/mcp55.c +++ b/southbridge/nvidia/mcp55/mcp55.c @@ -248,6 +248,18 @@ static void mcp55_enable(struct device *dev) } +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +/** MCP55 specific device operation for PCI devices. */ +struct pci_operations mcp55_pci_dev_ops_pci = { + .set_subsystem = mcp55_pci_dev_set_subsystem, +}; + struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, diff --git a/southbridge/nvidia/mcp55/mcp55.h b/southbridge/nvidia/mcp55/mcp55.h index ba5bfefd81..b199eca461 100644 --- a/southbridge/nvidia/mcp55/mcp55.h +++ b/southbridge/nvidia/mcp55/mcp55.h @@ -22,6 +22,10 @@ #ifndef MCP55_H #define MCP55_H +#define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40 +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); +struct pci_operations mcp55_pci_dev_ops_pci; #endif /* MCP55_H */ diff --git a/southbridge/nvidia/mcp55/pci.c b/southbridge/nvidia/mcp55/pci.c index 97a406bba7..df61516616 100644 --- a/southbridge/nvidia/mcp55/pci.c +++ b/southbridge/nvidia/mcp55/pci.c @@ -99,5 +99,5 @@ struct device_operations mcp55_pci = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; diff --git a/southbridge/nvidia/mcp55/pcie.c b/southbridge/nvidia/mcp55/pcie.c index 6388e85d12..5b5a2c3a48 100644 --- a/southbridge/nvidia/mcp55/pcie.c +++ b/southbridge/nvidia/mcp55/pcie.c @@ -57,7 +57,7 @@ struct device_operations mcp55_pcie_a = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_b_c = { @@ -71,7 +71,7 @@ struct device_operations mcp55_pcie_b_c = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_d = { @@ -85,7 +85,7 @@ struct device_operations mcp55_pcie_d = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_e = { @@ -99,7 +99,7 @@ struct device_operations mcp55_pcie_e = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_f = { @@ -113,5 +113,5 @@ struct device_operations mcp55_pcie_f = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; diff --git a/southbridge/nvidia/mcp55/sata.c b/southbridge/nvidia/mcp55/sata.c index f247b4583c..1df2169ed9 100644 --- a/southbridge/nvidia/mcp55/sata.c +++ b/southbridge/nvidia/mcp55/sata.c @@ -67,13 +67,6 @@ static void sata_init(struct device *dev) dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); - - -#warning finish set subsystem in mcp55 sata -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_sata = { @@ -86,5 +79,5 @@ struct device_operations mcp55_sata = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; diff --git a/southbridge/nvidia/mcp55/smbus.c b/southbridge/nvidia/mcp55/smbus.c index 2ac91220f1..a83df66572 100644 --- a/southbridge/nvidia/mcp55/smbus.c +++ b/southbridge/nvidia/mcp55/smbus.c @@ -127,24 +127,19 @@ static void mcp55_sm_init(struct device *dev) if (res) pm_base = res->base; #endif -#warning finish subsystem set in mcp55 smbus -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = mcp55_sm_init, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .phase6_init = mcp55_sm_init, + .ops_pci = &mcp55_pci_dev_ops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/southbridge/nvidia/mcp55/usb.c b/southbridge/nvidia/mcp55/usb.c index 61698ecd21..7b5c1705fc 100644 --- a/southbridge/nvidia/mcp55/usb.c +++ b/southbridge/nvidia/mcp55/usb.c @@ -34,11 +34,6 @@ static void usb_init(struct device * dev) { -#warning handle subsystem set in mcp55 usb -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_usb = { @@ -51,5 +46,5 @@ struct device_operations mcp55_usb = { .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; diff --git a/southbridge/nvidia/mcp55/usb2.c b/southbridge/nvidia/mcp55/usb2.c index 87117c263c..6ba3c103e7 100644 --- a/southbridge/nvidia/mcp55/usb2.c +++ b/southbridge/nvidia/mcp55/usb2.c @@ -44,11 +44,6 @@ static void usb2_init(struct device *dev) dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); -#warning mange set subsystem in mcp55 usb2 -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } static void usb2_set_resources(struct device *dev) @@ -84,5 +79,5 @@ struct device_operations mcp55_usb2 = { .phase4_set_resources = usb2_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb2_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, };