mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
If you get a warning, it's because you SHOULD be getting a warning.
next step is to fix up this: LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. Error adding the bootblock to the LAR. make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 1 make: exit 2 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
f28a44eb48
commit
159354e6ba
8 changed files with 24 additions and 27 deletions
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@ -117,18 +117,19 @@ struct ht_link {
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static int ht_setup_link(struct ht_link *prev, struct device *dev,
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unsigned int pos)
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{
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static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
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static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
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struct ht_link cur[1];
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int reset_needed;
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int linkb_to_host;
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#if OPT_HT_LINK == 1
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unsigned int present_width_cap, upstream_width_cap;
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unsigned int present_freq_cap, upstream_freq_cap;
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static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
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static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
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unsigned int ln_present_width_in, ln_upstream_width_in;
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unsigned int ln_present_width_out, ln_upstream_width_out;
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unsigned int freq, old_freq;
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unsigned int present_width, upstream_width, old_width;
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int reset_needed;
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int linkb_to_host;
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#endif
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/* Set the hypertransport link width and frequency. */
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reset_needed = 0;
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/* See which side of the device our previous write to
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@ -24,3 +24,4 @@
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#define CPU_SOCKET_TYPE SOCKET_AM2
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#define MEM_TRAIN_SEQ 0 /* for now */
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#define HW_MEM_HOLE_SIZE_AUTO_INC 0
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#define HW_MEM_HOLE_SIZEK 0x100000
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@ -1644,13 +1644,12 @@ void coherent_ht_finalize(unsigned nodes)
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printk(BIOS_SPEW, "done\r\n");
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}
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int apply_cpu_errata_fixes(unsigned nodes)
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int apply_cpu_errata_fixes(unsigned int nodes)
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{
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unsigned node;
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int needs_reset = 0;
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for(node = 0; node < nodes; node++) {
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u32 dev;
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u32 cmd;
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dev = NODE_MC(node);
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}
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return needs_reset;
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@ -126,7 +126,7 @@ static void k8_pci_domain_read_resources(struct device * dev)
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}
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}
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}
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#if CONFIG_PCI_64BIT_PREF_MEM == 0
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#ifdef CONFIG_PCI_64BIT_PREF_MEM
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->base = 0x400;
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@ -171,7 +171,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
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void disable_hoist_memory(unsigned long hole_startk, int i);
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u32 hoist_memory(unsigned long hole_startk, int i);
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#endif
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#if CONFIG_PCI_64BIT_PREF_MEM == 1
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#ifdef CONFIG_PCI_64BIT_PREF_MEM
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struct resource *io, *mem1, *mem2;
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struct resource *resource, *last;
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#endif
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@ -188,7 +188,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
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io = find_resource(dev, 0);
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io->base = DEVICE_IO_START;
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#endif
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#if CONFIG_PCI_64BIT_PREF_MEM == 1
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#ifdef CONFIG_PCI_64BIT_PREF_MEM
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/* Now reallocate the pci resources memory with the
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* highest addresses I can manage.
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*/
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@ -330,7 +330,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
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}
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printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08lx, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
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printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
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/* See if I need to split the region to accomodate pci memory space */
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if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
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@ -394,8 +394,6 @@ void ht_setup_chainx(u32 bdf, u8 upos, u8 bus,
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u8 next_unitid, last_unitid;
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unsigned uoffs;
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int reset_needed = 0;
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#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
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/* let's record the device of last ht device,
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* So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
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@ -519,7 +517,9 @@ void ht_setup_chainx(u32 bdf, u8 upos, u8 bus,
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} while (last_unitid != next_unitid );
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#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
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out:
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#endif
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end_of_chain: ;
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#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
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@ -718,7 +718,6 @@ static void ht_setup_chains(u8 ht_c_num, struct sys_info *sysinfo)
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unsigned regpos;
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u32 dword;
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u8 busn;
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unsigned bus;
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unsigned offset_unitid = 0;
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reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4);
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@ -2264,8 +2264,6 @@ void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo
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{
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u32 dword;
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u32 dwordx;
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unsigned SlowAccessMode = 0;
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long dimm_mask = meminfo->dimm_mask & 0x0f;
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#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */
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@ -2293,6 +2291,7 @@ void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo
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#endif
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#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
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unsigned SlowAccessMode = 0;
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/* for UNBUF DIMM */
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dword = 0x00111222;
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dwordx = 0x002f2f00;
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@ -2531,7 +2530,7 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info
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#endif
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meminfo = &sysinfo->meminfo[ctrl->node_id];
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printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :0x%x\n", paramx);
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printk(BIOS_DEBUG, "FIXME sdram_set_spd_registers: paramx :%p\n", ¶mx);
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activate_spd_rom(ctrl);
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dimm_mask = spd_detect_dimms(ctrl);
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@ -2749,7 +2748,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
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print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
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#endif
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u32 dword;
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/* Error if I don't have memory */
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if (memory_end_k(ctrl, controllers) == 0) {
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@ -2758,7 +2756,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
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/* Before enabling memory start the memory clocks */
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for(i = 0; i < controllers; i++) {
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u32 dtl, dch;
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u32 dch;
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if (!sysinfo->ctrl_present[ i ])
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continue;
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dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
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@ -2779,11 +2777,10 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
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/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
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memreset(controllers, ctrl);
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#if 0
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#if 1
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printk(BIOS_DEBUG, "prepare to InitDram:");
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for(i=0; i<10; i++) {
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print_debug_hex32(i);
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printk(BIOS_DEBUG, "\b\b\b\b\b\b\b\b");
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printk(BIOS_DEBUG, "%08x\b\b\b\b\b\b\b\b", i);
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}
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printk(BIOS_DEBUG, "\n");
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#endif
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@ -2839,7 +2836,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
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}
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for(i = 0; i < controllers; i++) {
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u32 dcl, dch, dcm;
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u32 dcl, dcm;
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if (!sysinfo->ctrl_present[ i ])
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continue;
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/* Skip everything if I don't have any memory on this controller */
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@ -100,12 +100,12 @@ unsigned pm_base;
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static void acpi_init(struct device *dev)
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{
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u8 byte;
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u16 word;
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u16 pm10_bar;
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u32 dword;
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int on;
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#if 0
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u16 word;
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printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
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byte = pci_read_config8(dev, 0x49);
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pci_write_config8(dev, 0x49, byte | (1<<2));
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@ -94,7 +94,7 @@ static void setup_ioapic(void)
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l = (unsigned long *) ioapic_base;
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ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
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printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid);
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printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid);
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for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
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i++, a++) {
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@ -119,7 +119,7 @@ static void enable_hpet(struct device *dev)
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pci_write_config32(dev,0xa0, 0xfed00001);
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hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
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printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
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printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
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}
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