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If you get a warning, it's because you SHOULD be getting a warning.

Browse source 
next step is to fix up this:
   LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1
make: exit 2

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-24 03:27:28 +00:00
parent f28a44eb48
commit 159354e6ba
8 changed files with 24 additions and 27 deletions
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11
device/hypertransport.c
View file

@ -117,18 +117,19 @@ struct ht_link {
static int ht_setup_link(struct ht_link *prev, struct device *dev, static int ht_setup_link(struct ht_link *prev, struct device *dev,
unsigned int pos) unsigned int pos)
{ {
static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
struct ht_link cur[1]; struct ht_link cur[1];
int reset_needed;
int linkb_to_host;
#if OPT_HT_LINK == 1
unsigned int present_width_cap, upstream_width_cap; unsigned int present_width_cap, upstream_width_cap;
unsigned int present_freq_cap, upstream_freq_cap; unsigned int present_freq_cap, upstream_freq_cap;
static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
unsigned int ln_present_width_in, ln_upstream_width_in; unsigned int ln_present_width_in, ln_upstream_width_in;
unsigned int ln_present_width_out, ln_upstream_width_out; unsigned int ln_present_width_out, ln_upstream_width_out;
unsigned int freq, old_freq; unsigned int freq, old_freq;
unsigned int present_width, upstream_width, old_width; unsigned int present_width, upstream_width, old_width;
int reset_needed; #endif
int linkb_to_host;
/* Set the hypertransport link width and frequency. */ /* Set the hypertransport link width and frequency. */
reset_needed = 0; reset_needed = 0;
/* See which side of the device our previous write to /* See which side of the device our previous write to

1
mainboard/amd/serengeti/mainboard.h
View file

@ -24,3 +24,4 @@
#define CPU_SOCKET_TYPE SOCKET_AM2 #define CPU_SOCKET_TYPE SOCKET_AM2
#define MEM_TRAIN_SEQ 0 /* for now */ #define MEM_TRAIN_SEQ 0 /* for now */
#define HW_MEM_HOLE_SIZE_AUTO_INC 0 #define HW_MEM_HOLE_SIZE_AUTO_INC 0
#define HW_MEM_HOLE_SIZEK 0x100000

3
northbridge/amd/k8/coherent_ht.c
View file

@ -1644,13 +1644,12 @@ void coherent_ht_finalize(unsigned nodes)
printk(BIOS_SPEW, "done\r\n"); printk(BIOS_SPEW, "done\r\n");
} }
int apply_cpu_errata_fixes(unsigned nodes) int apply_cpu_errata_fixes(unsigned int nodes)
{ {
unsigned node; unsigned node;
int needs_reset = 0; int needs_reset = 0;
for(node = 0; node < nodes; node++) { for(node = 0; node < nodes; node++) {
u32 dev; u32 dev;
u32 cmd;
dev = NODE_MC(node); dev = NODE_MC(node);
} }
return needs_reset; return needs_reset;

8
northbridge/amd/k8/domain.c
View file

@ -126,7 +126,7 @@ static void k8_pci_domain_read_resources(struct device * dev)
} }
} }
} }
#if CONFIG_PCI_64BIT_PREF_MEM == 0 #ifdef CONFIG_PCI_64BIT_PREF_MEM
/* Initialize the system wide io space constraints */ /* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400; resource->base = 0x400;
@ -171,7 +171,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
void disable_hoist_memory(unsigned long hole_startk, int i); void disable_hoist_memory(unsigned long hole_startk, int i);
u32 hoist_memory(unsigned long hole_startk, int i); u32 hoist_memory(unsigned long hole_startk, int i);
#endif #endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1 #ifdef CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2; struct resource *io, *mem1, *mem2;
struct resource *resource, *last; struct resource *resource, *last;
#endif #endif
@ -188,7 +188,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
io = find_resource(dev, 0); io = find_resource(dev, 0);
io->base = DEVICE_IO_START; io->base = DEVICE_IO_START;
#endif #endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1 #ifdef CONFIG_PCI_64BIT_PREF_MEM
/* Now reallocate the pci resources memory with the /* Now reallocate the pci resources memory with the
* highest addresses I can manage. * highest addresses I can manage.
*/ */
@ -330,7 +330,7 @@ static void k8_pci_domain_set_resources(struct device * dev)
} }
printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08lx, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
/* See if I need to split the region to accomodate pci memory space */ /* See if I need to split the region to accomodate pci memory space */
if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {

5
northbridge/amd/k8/incoherent_ht.c
View file

@ -394,8 +394,6 @@ void ht_setup_chainx(u32 bdf, u8 upos, u8 bus,
u8 next_unitid, last_unitid; u8 next_unitid, last_unitid;
unsigned uoffs; unsigned uoffs;
int reset_needed = 0;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
/* let's record the device of last ht device, /* let's record the device of last ht device,
* So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE * So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
@ -519,7 +517,9 @@ void ht_setup_chainx(u32 bdf, u8 upos, u8 bus,
} while (last_unitid != next_unitid ); } while (last_unitid != next_unitid );
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
out: out:
#endif
end_of_chain: ; end_of_chain: ;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
@ -718,7 +718,6 @@ static void ht_setup_chains(u8 ht_c_num, struct sys_info *sysinfo)
unsigned regpos; unsigned regpos;
u32 dword; u32 dword;
u8 busn; u8 busn;
unsigned bus;
unsigned offset_unitid = 0; unsigned offset_unitid = 0;
reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4);

17
northbridge/amd/k8/raminit.c
View file

@ -2264,8 +2264,6 @@ void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo
{ {
u32 dword; u32 dword;
u32 dwordx; u32 dwordx;
unsigned SlowAccessMode = 0;
long dimm_mask = meminfo->dimm_mask & 0x0f; long dimm_mask = meminfo->dimm_mask & 0x0f;
#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ #if DIMM_SUPPORT==0x0104 /* DDR2 and REG */
@ -2293,7 +2291,8 @@ void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo
#endif #endif
#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ #if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
/* for UNBUF DIMM */ unsigned SlowAccessMode = 0;
/* for UNBUF DIMM */
dword = 0x00111222; dword = 0x00111222;
dwordx = 0x002f2f00; dwordx = 0x002f2f00;
switch (meminfo->memclk_set) { switch (meminfo->memclk_set) {
@ -2531,7 +2530,7 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info
#endif #endif
meminfo = &sysinfo->meminfo[ctrl->node_id]; meminfo = &sysinfo->meminfo[ctrl->node_id];
printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :0x%x\n", paramx); printk(BIOS_DEBUG, "FIXME sdram_set_spd_registers: paramx :%p\n", &paramx);
activate_spd_rom(ctrl); activate_spd_rom(ctrl);
dimm_mask = spd_detect_dimms(ctrl); dimm_mask = spd_detect_dimms(ctrl);
@ -2749,7 +2748,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]); print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
#endif #endif
u32 dword;
/* Error if I don't have memory */ /* Error if I don't have memory */
if (memory_end_k(ctrl, controllers) == 0) { if (memory_end_k(ctrl, controllers) == 0) {
@ -2758,7 +2756,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
/* Before enabling memory start the memory clocks */ /* Before enabling memory start the memory clocks */
for(i = 0; i < controllers; i++) { for(i = 0; i < controllers; i++) {
u32 dtl, dch; u32 dch;
if (!sysinfo->ctrl_present[ i ]) if (!sysinfo->ctrl_present[ i ])
continue; continue;
dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
@ -2779,11 +2777,10 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
/* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */ /* We need to wait a mimmium of 20 MEMCLKS to enable the InitDram */
memreset(controllers, ctrl); memreset(controllers, ctrl);
#if 0 #if 1
printk(BIOS_DEBUG, "prepare to InitDram:"); printk(BIOS_DEBUG, "prepare to InitDram:");
for(i=0; i<10; i++) { for(i=0; i<10; i++) {
print_debug_hex32(i); printk(BIOS_DEBUG, "%08x\b\b\b\b\b\b\b\b", i);
printk(BIOS_DEBUG, "\b\b\b\b\b\b\b\b");
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
#endif #endif
@ -2839,7 +2836,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys
} }
for(i = 0; i < controllers; i++) { for(i = 0; i < controllers; i++) {
u32 dcl, dch, dcm; u32 dcl, dcm;
if (!sysinfo->ctrl_present[ i ]) if (!sysinfo->ctrl_present[ i ])
continue; continue;
/* Skip everything if I don't have any memory on this controller */ /* Skip everything if I don't have any memory on this controller */

2
southbridge/amd/amd8111/acpi.c
View file

@ -100,12 +100,12 @@ unsigned pm_base;
static void acpi_init(struct device *dev) static void acpi_init(struct device *dev)
{ {
u8 byte; u8 byte;
u16 word;
u16 pm10_bar; u16 pm10_bar;
u32 dword; u32 dword;
int on; int on;
#if 0 #if 0
u16 word;
printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
byte = pci_read_config8(dev, 0x49); byte = pci_read_config8(dev, 0x49);
pci_write_config8(dev, 0x49, byte | (1<<2)); pci_write_config8(dev, 0x49, byte | (1<<2));

4
southbridge/amd/amd8111/lpc.c
View file

@ -94,7 +94,7 @@ static void setup_ioapic(void)
l = (unsigned long *) ioapic_base; l = (unsigned long *) ioapic_base;
ioapicregvalues[0].value_high = bsp_apicid<<(56-32); ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02lx\n", bsp_apicid);
for (i = 0; i < ARRAY_SIZE(ioapicregvalues); for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
i++, a++) { i++, a++) {
@ -119,7 +119,7 @@ static void enable_hpet(struct device *dev)
pci_write_config32(dev,0xa0, 0xfed00001); pci_write_config32(dev,0xa0, 0xfed00001);
hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe;
printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
} }