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UPSTREAM: device/dram/ddr2.c: Fix is_registered_ddr2
Type 0x10 is mini RDIMM according to JEDEC DDR2 SPD
specifications.
BUG=none
BRANCH=none
TEST=none
Change-Id: I35c9634f36868caf03438e688c1ec5ab484c2449
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 87f7588c50
Original-Change-Id: I6d35bd74961326ebd9225f044313b107aca24bda
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20058
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/531195
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
parent
3059447687
commit
15501025ec
2 changed files with 3 additions and 2 deletions
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@ -39,7 +39,8 @@
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int spd_dimm_is_registered_ddr2(enum spd_dimm_type type)
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{
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if ((type == SPD_DIMM_TYPE_RDIMM)
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| (type == SPD_DIMM_TYPE_72B_SO_RDIMM))
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|| (type == SPD_DIMM_TYPE_72B_SO_RDIMM)
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|| (type == SPD_DIMM_TYPE_MINI_RDIMM))
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return 1;
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return 0;
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@ -75,7 +75,7 @@ enum spd_dimm_type {
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SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06,
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SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07,
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SPD_DIMM_TYPE_MICRO_DIMM = 0x08,
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SPD_DIMM_TYPE_MINI_DIMM = 0x10,
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SPD_DIMM_TYPE_MINI_RDIMM = 0x10,
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SPD_DIMM_TYPE_MINI_UDIMM = 0x20,
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/* Masks to bits 5:0 to give the dimm type */
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SPD_DIMM_TYPE_MASK = 0x3f,
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