mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
These changes get us past stage0, past stage1, and into the search for a
file in LAR called raminit. The intent is that stage0_i586.S would be common for just about all stage0. It has no includes. We had to go with an ldscript.ld to deal with the many bugs in binutils. Maybe someday this will change. Tested by Ron and Uwe in bochs with debugging. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@68 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
f4d7429c5c
commit
1492bdbd5c
3 changed files with 621 additions and 19 deletions
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@ -2,6 +2,7 @@
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## This file is part of the LinuxBIOS project.
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## This file is part of the LinuxBIOS project.
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##
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##
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## Copyright (C) 2006 coresystems GmbH
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## Copyright (C) 2006 coresystems GmbH
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## Copyright (C) 2007 Ron G. Minnich <rminnich@gmail.com>
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##
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##
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## This program is free software; you can redistribute it and/or modify
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## it under the terms of the GNU General Public License as published by
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@ -26,13 +27,13 @@
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CFLAGS :=
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CFLAGS :=
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linuxbios.jump: FORCE
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#linuxbios.jump: FORCE
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$(Q)echo "Building jump vector"
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# $(Q)echo "Building jump vector"
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$(Q)$(CC) -E $(srctree)/arch/x86/reset.S -o $(objtree)/reset.s -DBOOTBLK=0x1f00 -DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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# $(Q)$(CC) -E $(srctree)/arch/x86/reset.S -o $(objtree)/reset.s -DBOOTBLK=0x1f00 -DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)$(AS) $(objtree)/reset.s -o $(objtree)/reset.o
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# $(Q)$(AS) $(objtree)/reset.s -o $(objtree)/reset.o
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$(Q)$(LD) -Ttext 0xfffffff0 -s --oformat binary $(objtree)/reset.o -o $(objtree)/linuxbios.jump
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# $(Q)$(LD) -Ttext 0xfffffff0 -s --oformat binary $(objtree)/reset.o -o $(objtree)/linuxbios.jump
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$(Q)chmod 644 $(objtree)/linuxbios.jump
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# $(Q)chmod 644 $(objtree)/linuxbios.jump
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$(Q)echo "Len: `wc -c < linuxbios.jump`"
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# $(Q)echo "Len: `wc -c < linuxbios.jump`"
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#
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#
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# This part takes care of compression. It should build the compression modules
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# This part takes care of compression. It should build the compression modules
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@ -92,12 +93,19 @@ linuxbios.lar: $(objtree)/lar lzma linuxbios.initram linuxbios_ram payload
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INITCFLAGS=-I$(srctree)/include/cpu/generic/x86 -I$(srctree)/include -fno-builtin -Os
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INITCFLAGS=-I$(srctree)/include/cpu/generic/x86 -I$(srctree)/include -fno-builtin -Os
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linuxbios.init:
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# Note: we could cat .o files together, but one important goal is to leave us with a complete gdb-debuggable
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# .o for use with popular ICE and other tools. We go to some effort here to end up with a
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# stage0.o that has debug symbols. This stage0 will actually load the first LAR file and execute it.
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stage0.init:
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echo "You will need to create variables for arch/$(CONFIG_ARCH)"
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echo "and CC flags for architecture, and to select the stage0_$(CONFIG_STAGE0_1)"
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echo "these will be set in mainboard Kconfig. Also, you need to define the .c files for "
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echo "stage0 in that file as well. "
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$(Q)echo Building linuxbios.init
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$(Q)echo Building linuxbios.init
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#
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#
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# asm stub
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# asm stub
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$(Q)$(CC) -E $(srctree)/arch/x86/init.S -o $(objtree)/init.s
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$(Q)$(CC) -E $(LINUXBIOSINCLUDE) $(srctree)/arch/x86/stage0_i586.S -o $(objtree)/stage0_i586.s -DBOOTBLK=0x1f00 -DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)$(AS) $(objtree)/init.s -o $(objtree)/init.o
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$(Q)$(AS) $(objtree)/stage0_i586.s -o $(objtree)/stage0_i586.o
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#
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#
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# main
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# main
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$(Q)$(CC) $(INITCFLAGS) -c $(srctree)/arch/x86/cachemain.c -o cachemain.o
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$(Q)$(CC) $(INITCFLAGS) -c $(srctree)/arch/x86/cachemain.c -o cachemain.o
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@ -110,23 +118,28 @@ linuxbios.init:
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$(Q)$(CC) $(INITCFLAGS) -c $(srctree)/console/vtxprintf.c -o vtxprintf.o
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$(Q)$(CC) $(INITCFLAGS) -c $(srctree)/console/vtxprintf.c -o vtxprintf.o
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$(Q)$(CC) $(INITCFLAGS) -c $(srctree)/lib/uart8250.c -o uart8250.o
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$(Q)$(CC) $(INITCFLAGS) -c $(srctree)/lib/uart8250.c -o uart8250.o
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# TODO: dynamic start address 4G - 0x2000 (bootblock size)
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# leave a .o around for debugging etc.
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$(Q)$(LD) -Ttext 0xffffe000 -s --oformat binary init.o cachemain.o console.o uart8250.o \
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# we did not want to use a ldscript. But the outstanding bugs in gld make it impossible to do
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serial.o vtxprintf.o lar.o -o linuxbios.init.pre
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# anything else.
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# Google Not enough room for program headers (allocated 3, need 4)
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$(Q)$(CC) -m32 -nostdlib -static -T $(srctree)/arch/x86/ldscript.ld cachemain.o console.o uart8250.o \
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serial.o vtxprintf.o lar.o stage0_i586.o -o stage0.o
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$(Q)objcopy -O binary stage0.o stage0.init.pre
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# Pad boot block to 0x2000 - 0x100
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# Pad boot block to 0x2000 - 0x100
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$(Q)dd if=linuxbios.init.pre of=linuxbios.init bs=7936 conv=sync
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# we will probably remove this step -- not needed if we continue with ldscript.ld
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$(Q)echo "Len: `wc -c < linuxbios.init.pre`"
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$(Q)dd if=stage0.init.pre of=stage0.init bs=7936 conv=sync
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$(Q)echo "Len: `wc -c < stage0.init.pre`"
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#
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#
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$(Q)test `wc -c < linuxbios.init.pre` -gt 7936 && echo "Error. Bootblock got too big" || true
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$(Q)test `wc -c < stage0.init.pre` -gt 7936 && echo "Error. Bootblock got too big" || true
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#
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#
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# Compose the image:
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# Compose the image:
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#
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#
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linuxbios.rom: linuxbios.lar linuxbios.init linuxbios.vpd linuxbios.jump
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linuxbios.rom: linuxbios.lar stage0.init linuxbios.vpd
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$(Q)cat $(objtree)/linuxbios.lar $(objtree)/linuxbios.init \
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$(Q)cat $(objtree)/linuxbios.lar \
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$(objtree)/linuxbios.vpd $(objtree)/linuxbios.jump > \
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$(objtree)/linuxbios.vpd $(objtree)/stage0.init> \
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$(objtree)/linuxbios.rom
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$(objtree)/linuxbios.rom
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$(objtree)/lar:
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$(objtree)/lar:
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61
arch/x86/ldscript.ld
Normal file
61
arch/x86/ldscript.ld
Normal file
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@ -0,0 +1,61 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Ron G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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ENTRY(_start)
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*/
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TARGET(binary)
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SECTIONS
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{
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. = 0xffffe000 + 256; /* leave space for vpd */
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.stage0_1 . : {
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_stage0_1 = .;
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*(.text);
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*(.data);
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*(.bss);
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*(.rodata.*)
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*(.rodata)
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_estage0_1 = .;
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}
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/DISCARD/ : {
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*(.comment)
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*(.note)
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}
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}
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SECTIONS {
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_ROMTOP = 0xfffffff0;
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. = _ROMTOP;
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.resetvector . : {
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*(.reset)
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/*
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. = 15 ;
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BYTE(0x00);
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*/
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}
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}
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/*
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*/
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528
arch/x86/stage0_i586.S
Normal file
528
arch/x86/stage0_i586.S
Normal file
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@ -0,0 +1,528 @@
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## Note: this file contains _multiple_ copyright/license headers, see below.
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##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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##
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## Copyright (C) 2007 coresystems GmbH
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## Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# init code - switch cpu to pmode and enable cache as ram.
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#include "macros.h"
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#define ROM_CODE_SEG 0x08
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#define ROM_DATA_SEG 0x10
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#define CACHE_RAM_CODE_SEG 0x18
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#define CACHE_RAM_DATA_SEG 0x20
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# .section ".rom.text"
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.code16
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#.=0
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.globl _stage0
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# .section ".rom.text"
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_stage0:
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cli
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/* save the BIST result */
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movl %eax, %ebp;
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/* thanks to kmliu@sis.tw.com for this TBL fix */
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/* IMMEDIATELY invalidate the translation lookaside buffer before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB */
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/* switch to protected mode */
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/* NOTE: WIth GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) using BFD version 2.15.94.0.2.2 20041220
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* this works fine without all the ld hackery and other things. So leave it as is with this comment.
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*/
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# movw %cs, %ax
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# shlw $4, %ax
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# movl $0xffffe000, %ebx
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# movw $gdt16 + 0xe000, %bx
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#subw %ax, %bx
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#data32 lgdt %cs:(%bx)
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data32 lgdt %cs:gdtptr
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST result */
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movl %ebp, %eax
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// port80_post (0x23) /* post 0x01 */
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/* Now we are in protected mode. Jump to a 32 bit code segment. */
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data32 ljmp $ROM_CODE_SEG, $protected_stage0
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/* I am leaving this weird jump in here in the event that future gas bugs force it to be used. */
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#.byte 0x66
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.code32
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#ljmp $ROM_CODE_SEG, $protected_stage0
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#.code16
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.align 4
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.globl gdt16
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gdt16 = . - _stage0
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gdt16x:
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.word gdt16xend - gdt16x -1 /* compute the table limit */
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.long gdt16x
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt16xend:
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/* From now on we are 32bit */
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.code32
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/* We have two gdts where we could have one. That is ok.
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* Let's not worry about this -- optimizing gdt is pointless since we're only in it for a little bit.
|
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* BTW note the trick below: the gdt points to ITSELF, and the first good descriptor is at offset 8.
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* so you word-align the table, and then because you chose 8,
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|
* you get a nice 64-bit aligned gdt endtry, which is
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* good as this is the size of the entry. Just in case you ever wonder why people do this.
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||||||
|
*/
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||||||
|
.align 4
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||||||
|
.globl gdtptr
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|
gdt:
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||||||
|
gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
|
||||||
|
.long gdt /* we know the offset */
|
||||||
|
.word 0
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||||||
|
|
||||||
|
/* selgdt 0x08, flat code segment */
|
||||||
|
.word 0xffff, 0x0000
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||||||
|
.byte 0x00, 0x9b, 0xcf, 0x00
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||||||
|
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||||||
|
/* selgdt 0x10,flat data segment */
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||||||
|
.word 0xffff, 0x0000
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||||||
|
.byte 0x00, 0x93, 0xcf, 0x00
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||||||
|
|
||||||
|
/* selgdt 0x18, flat code segment for CAR */
|
||||||
|
.word 0xffff, 0x0000
|
||||||
|
.byte 0x00, 0x9b, 0xcf, 0x00
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||||||
|
|
||||||
|
/* selgdt 0x20,flat data segment for CAR */
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||||||
|
.word 0xffff, 0x0000
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||||||
|
.byte 0x00, 0x93, 0xcf, 0x00
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||||||
|
gdt_end:
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When we come here we are in protected mode. We expand
|
||||||
|
* the stack and copies the data segment from ROM to the
|
||||||
|
* memory.
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||||||
|
*
|
||||||
|
* After that, we call the chipset bootstrap routine that
|
||||||
|
* does what is left of the chipset initialization.
|
||||||
|
*
|
||||||
|
* NOTE aligned to 4 so that we are sure that the prefetch
|
||||||
|
* cache will be reloaded.
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||||||
|
*/
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||||||
|
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||||||
|
.align 4
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|
.globl protected_stage0
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|
protected_stage0:
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//This code was used by v2. TODO
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|
lgdt %cs:gdtptr
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|
ljmp $ROM_CODE_SEG, $__protected_stage0
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|
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||||||
|
.globl __protected_stage0
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|
__protected_stage0:
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/* Save the BIST value */
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||||||
|
movl %eax, %ebp
|
||||||
|
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||||||
|
port80_post (0x01) /* post 0x01 */
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||||||
|
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||||||
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movw $ROM_DATA_SEG, %ax
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||||||
|
movw %ax, %ds
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||||||
|
movw %ax, %es
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||||||
|
movw %ax, %ss
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||||||
|
movw %ax, %fs
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||||||
|
movw %ax, %gs
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||||||
|
|
||||||
|
/* Restore the BIST value to %eax */
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||||||
|
movl %ebp, %eax
|
||||||
|
|
||||||
|
.align 4
|
||||||
|
|
||||||
|
##
|
||||||
|
## This file is part of the LinuxBIOS project.
|
||||||
|
##
|
||||||
|
## Copyright (C) 2005 Eswar Nallusamy, LANL
|
||||||
|
##
|
||||||
|
## Copyright (C) 2005 Tyan
|
||||||
|
## Written by Yinghai Lu <yhlu@tyan.com> for Tyan.
|
||||||
|
##
|
||||||
|
## Copyright (C) 2007 coresystems GmbH
|
||||||
|
## Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH
|
||||||
|
##
|
||||||
|
## This program is free software; you can redistribute it and/or modify
|
||||||
|
## it under the terms of the GNU General Public License as published by
|
||||||
|
## the Free Software Foundation; either version 2 of the License, or
|
||||||
|
## (at your option) any later version.
|
||||||
|
##
|
||||||
|
## This program is distributed in the hope that it will be useful,
|
||||||
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
## GNU General Public License for more details.
|
||||||
|
##
|
||||||
|
## You should have received a copy of the GNU General Public License
|
||||||
|
## along with this program; if not, write to the Free Software
|
||||||
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
##
|
||||||
|
|
||||||
|
/* We will use 4Kbytes only for cache as ram. This is
|
||||||
|
* enough to fit in our stack.
|
||||||
|
*
|
||||||
|
* disable HyperThreading is done by eswar
|
||||||
|
* the other is very similar to the AMD CAR, except remove amd specific msr
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CONFIG_CARSIZE
|
||||||
|
#define CacheSize 4096
|
||||||
|
#else
|
||||||
|
#define CacheSize CONFIG_CARSIZE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CONFIG_CARBASE
|
||||||
|
#define CacheBase (0xd0000 - CacheSize)
|
||||||
|
#else
|
||||||
|
#define CacheBase CONFIG_CARBASE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define ASSEMBLY
|
||||||
|
#include "mtrr.h"
|
||||||
|
|
||||||
|
/* Save the BIST result */
|
||||||
|
movl %eax, %ebp
|
||||||
|
|
||||||
|
CacheAsRam:
|
||||||
|
/* Check whether the processor has HT capability */
|
||||||
|
movl $01, %eax
|
||||||
|
cpuid
|
||||||
|
btl $28, %edx
|
||||||
|
jnc NotHtProcessor
|
||||||
|
bswapl %ebx
|
||||||
|
cmpb $01, %bh
|
||||||
|
jbe NotHtProcessor
|
||||||
|
|
||||||
|
/* It is a HT processor; Send SIPI to the other logical processor
|
||||||
|
* within this processor so that the CAR related common system
|
||||||
|
* registers are programmed accordingly
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Use some register that is common to both logical processors
|
||||||
|
* as semaphore. Refer Appendix B, Vol.3
|
||||||
|
*/
|
||||||
|
|
||||||
|
xorl %eax, %eax
|
||||||
|
xorl %edx, %edx
|
||||||
|
movl $0x250, %ecx
|
||||||
|
wrmsr
|
||||||
|
|
||||||
|
/* Figure out the logical AP's APIC ID; the following logic will work
|
||||||
|
* only for processors with 2 threads.
|
||||||
|
*
|
||||||
|
* Refer to Vol 3. Table 7-1 for details about this logic
|
||||||
|
*/
|
||||||
|
movl $0xFEE00020, %esi
|
||||||
|
movl (%esi), %ebx
|
||||||
|
andl $0xFF000000, %ebx
|
||||||
|
bswapl %ebx
|
||||||
|
btl $0, %ebx
|
||||||
|
jnc LogicalAP0
|
||||||
|
andb $0xFE, %bl
|
||||||
|
jmp SendSIPI
|
||||||
|
LogicalAP0:
|
||||||
|
orb $0x01, %bl
|
||||||
|
SendSIPI:
|
||||||
|
bswapl %ebx /* ebx - logical AP's APIC ID */
|
||||||
|
|
||||||
|
/* Fill up the IPI command registers in the Local APIC mapped to
|
||||||
|
* default address and issue SIPI to the other logical processor
|
||||||
|
* within this processor die.
|
||||||
|
*/
|
||||||
|
|
||||||
|
RetrySIPI:
|
||||||
|
movl %ebx, %eax
|
||||||
|
movl $0xFEE00310, %esi
|
||||||
|
movl %eax, (%esi)
|
||||||
|
|
||||||
|
/* SIPI vector - F900:0000 */
|
||||||
|
movl $0x000006F9, %eax
|
||||||
|
movl $0xFEE00300, %esi
|
||||||
|
movl %eax, (%esi)
|
||||||
|
|
||||||
|
movl $0x30, %ecx
|
||||||
|
SIPIDelay:
|
||||||
|
pause
|
||||||
|
decl %ecx
|
||||||
|
jnz SIPIDelay
|
||||||
|
|
||||||
|
movl (%esi), %eax
|
||||||
|
andl $0x00001000, %eax
|
||||||
|
jnz RetrySIPI
|
||||||
|
|
||||||
|
/* Wait for the Logical AP to complete initialization */
|
||||||
|
LogicalAPSIPINotdone:
|
||||||
|
movl $0x250, %ecx
|
||||||
|
rdmsr
|
||||||
|
orl %eax, %eax
|
||||||
|
jz LogicalAPSIPINotdone
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
NotHtProcessor:
|
||||||
|
/* Set the default memory type and enable fixed and variable MTRRs */
|
||||||
|
movl $MTRRdefType_MSR, %ecx
|
||||||
|
xorl %edx, %edx
|
||||||
|
/* Enable Variable and Fixed MTRRs */
|
||||||
|
movl $0x00000c00, %eax
|
||||||
|
wrmsr
|
||||||
|
|
||||||
|
/*Clear all MTRRs */
|
||||||
|
xorl %edx, %edx
|
||||||
|
movl $fixed_mtrr_msr, %esi
|
||||||
|
clear_fixed_var_mtrr:
|
||||||
|
lodsl (%esi), %eax
|
||||||
|
testl %eax, %eax
|
||||||
|
jz clear_fixed_var_mtrr_out
|
||||||
|
|
||||||
|
movl %eax, %ecx
|
||||||
|
xorl %eax, %eax
|
||||||
|
wrmsr
|
||||||
|
|
||||||
|
jmp clear_fixed_var_mtrr
|
||||||
|
clear_fixed_var_mtrr_out:
|
||||||
|
|
||||||
|
#if CacheSize == 0x10000
|
||||||
|
/* enable caching for 64K using fixed mtrr */
|
||||||
|
movl $0x268, %ecx /* fix4k_c0000*/
|
||||||
|
movl $0x06060606, %eax /* WB IO type */
|
||||||
|
movl %eax, %edx
|
||||||
|
wrmsr
|
||||||
|
movl $0x269, %ecx
|
||||||
|
wrmsr
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if CacheSize == 0x8000
|
||||||
|
/* enable caching for 32K using fixed mtrr */
|
||||||
|
movl $0x269, %ecx /* fix4k_c8000*/
|
||||||
|
movl $0x06060606, %eax /* WB IO type */
|
||||||
|
movl %eax, %edx
|
||||||
|
wrmsr
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* enable caching for 16K/8K/4K using fixed mtrr */
|
||||||
|
movl $0x269, %ecx /* fix4k_cc000*/
|
||||||
|
#if CacheSize == 0x4000
|
||||||
|
movl $0x06060606, %edx /* WB IO type */
|
||||||
|
#endif
|
||||||
|
#if CacheSize == 0x2000
|
||||||
|
movl $0x06060000, %edx /* WB IO type */
|
||||||
|
#endif
|
||||||
|
#if CacheSize == 0x1000
|
||||||
|
movl $0x06000000, %edx /* WB IO type */
|
||||||
|
#endif
|
||||||
|
xorl %eax, %eax
|
||||||
|
wrmsr
|
||||||
|
|
||||||
|
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
|
||||||
|
/* enable write base caching so we can do execute in place
|
||||||
|
* on the flash rom.
|
||||||
|
*/
|
||||||
|
movl $0x202, %ecx
|
||||||
|
xorl %edx, %edx
|
||||||
|
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
|
||||||
|
wrmsr
|
||||||
|
|
||||||
|
movl $0x203, %ecx
|
||||||
|
movl $0x0000000f, %edx
|
||||||
|
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
|
||||||
|
wrmsr
|
||||||
|
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
|
||||||
|
|
||||||
|
/* enable cache */
|
||||||
|
movl %cr0, %eax
|
||||||
|
andl $0x9fffffff,%eax
|
||||||
|
movl %eax, %cr0
|
||||||
|
|
||||||
|
/* Read the range with lodsl*/
|
||||||
|
movl $CacheBase, %esi
|
||||||
|
cld
|
||||||
|
movl $(CacheSize>>2), %ecx
|
||||||
|
rep lodsl
|
||||||
|
|
||||||
|
/* Clear the range */
|
||||||
|
movl $CacheBase, %edi
|
||||||
|
movl $(CacheSize>>2), %ecx
|
||||||
|
xorl %eax, %eax
|
||||||
|
rep stosl
|
||||||
|
|
||||||
|
|
||||||
|
/* TODO: make this a config variable */
|
||||||
|
#if CONFIG_CARTEST
|
||||||
|
/* check the cache as ram */
|
||||||
|
movl $CacheBase, %esi
|
||||||
|
movl $(CacheSize>>2), %ecx
|
||||||
|
.xin1:
|
||||||
|
movl %esi, %eax
|
||||||
|
movl %eax, (%esi)
|
||||||
|
decl %ecx
|
||||||
|
je .xout1
|
||||||
|
add $4, %esi
|
||||||
|
jmp .xin1
|
||||||
|
.xout1:
|
||||||
|
|
||||||
|
movl $CacheBase, %esi
|
||||||
|
// movl $(CacheSize>>2), %ecx
|
||||||
|
movl $4, %ecx
|
||||||
|
.xin1x:
|
||||||
|
movl %esi, %eax
|
||||||
|
|
||||||
|
movl $0x4000, %edx
|
||||||
|
movb %ah, %al
|
||||||
|
.testx1:
|
||||||
|
outb %al, $0x80
|
||||||
|
decl %edx
|
||||||
|
jnz .testx1
|
||||||
|
|
||||||
|
movl (%esi), %eax
|
||||||
|
cmpb 0xff, %al
|
||||||
|
je .xin2 /* dont show */
|
||||||
|
|
||||||
|
movl $0x4000, %edx
|
||||||
|
.testx2:
|
||||||
|
outb %al, $0x80
|
||||||
|
decl %edx
|
||||||
|
jnz .testx2
|
||||||
|
|
||||||
|
.xin2: decl %ecx
|
||||||
|
je .xout1x
|
||||||
|
add $4, %esi
|
||||||
|
jmp .xin1x
|
||||||
|
.xout1x:
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
movl $(CacheBase+CacheSize-4), %eax
|
||||||
|
movl %eax, %esp
|
||||||
|
|
||||||
|
/* Load a different set of data segments */
|
||||||
|
movw $CACHE_RAM_DATA_SEG, %ax
|
||||||
|
movw %ax, %ds
|
||||||
|
movw %ax, %es
|
||||||
|
movw %ax, %ss
|
||||||
|
|
||||||
|
lout:
|
||||||
|
|
||||||
|
/* Restore the BIST result */
|
||||||
|
movl %ebp, %eax
|
||||||
|
/* We need to set ebp ? No need */
|
||||||
|
movl %esp, %ebp
|
||||||
|
pushl %eax /* bist */
|
||||||
|
call stage1_main
|
||||||
|
/* We will not go back */
|
||||||
|
fixed_mtrr_msr:
|
||||||
|
.long 0x250, 0x258, 0x259
|
||||||
|
.long 0x268, 0x269, 0x26A
|
||||||
|
.long 0x26B, 0x26C, 0x26D
|
||||||
|
.long 0x26E, 0x26F
|
||||||
|
var_mtrr_msr:
|
||||||
|
.long 0x200, 0x201, 0x202, 0x203
|
||||||
|
.long 0x204, 0x205, 0x206, 0x207
|
||||||
|
.long 0x208, 0x209, 0x20A, 0x20B
|
||||||
|
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||||
|
.long 0x000 /* NULL, end of table */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
##
|
||||||
|
## This file is part of the LinuxBIOS project.
|
||||||
|
##
|
||||||
|
## Copyright (C) 2007 coresystems GmbH
|
||||||
|
## Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH
|
||||||
|
##
|
||||||
|
## This program is free software; you can redistribute it and/or modify
|
||||||
|
## it under the terms of the GNU General Public License as published by
|
||||||
|
## the Free Software Foundation; either version 2 of the License, or
|
||||||
|
## (at your option) any later version.
|
||||||
|
##
|
||||||
|
## This program is distributed in the hope that it will be useful,
|
||||||
|
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
## GNU General Public License for more details.
|
||||||
|
##
|
||||||
|
## You should have received a copy of the GNU General Public License
|
||||||
|
## along with this program; if not, write to the Free Software
|
||||||
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
##
|
||||||
|
|
||||||
|
# reset vector
|
||||||
|
|
||||||
|
# RVECTOR: size of reset vector, default is 0x10
|
||||||
|
# RESRVED: size of vpd code, default is 0xf0
|
||||||
|
#
|
||||||
|
# BOOTBLK: size of bootblock code, default is 0x1f00 (8k-256b)
|
||||||
|
#
|
||||||
|
|
||||||
|
SEGMENT_SIZE = 0x10000
|
||||||
|
RVECTOR = 0x00010
|
||||||
|
#.=0x1ff0
|
||||||
|
#.=0xfffffff0
|
||||||
|
#.=_stage0 + 0x1ff0
|
||||||
|
# due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
|
||||||
|
# I think we should leave it this way forever, as the bugs come and go -- and come again
|
||||||
|
# .code16
|
||||||
|
# .section ".rom.text"
|
||||||
|
.section ".reset", "ax"
|
||||||
|
.globl _resetjump
|
||||||
|
_resetjump:
|
||||||
|
/* gnu bintools win again. this jumps to stage0 - 2. Sigh. */
|
||||||
|
# jmp _stage0
|
||||||
|
.byte 0xe9
|
||||||
|
.int _stage0 - ( . + 2 )
|
||||||
|
/* Note: The above jump is hand coded to work around bugs in binutils.
|
||||||
|
* 5 byte are used for a 3 byte instruction. This works because x86
|
||||||
|
* is little endian and allows us to use supported 32bit relocations
|
||||||
|
* instead of the weird 16 bit relocations that binutils does not
|
||||||
|
* handle consistenly between versions because they are used so rarely.
|
||||||
|
*/
|
||||||
|
.byte 0
|
||||||
|
|
||||||
|
# date? idstring? we might want to put something else in here.
|
||||||
|
.ascii DATE
|
||||||
|
|
||||||
|
# checksum
|
||||||
|
#.word 0
|
||||||
Loading…
Add table
Reference in a new issue