Fixes for various acer stuff. Also, you can now #ifdef out the real-mode stuff

in start32.inc.

romimages/RON_ASUS_CUA/Makefile

@@ -5,10 +5,12 @@ CPUFLAGS += -DINTEL_PPRO_MTRR
 CPUFLAGS += -DNEWPCI
 CPUFLAGS += -DSERIAL_CONSOLE
 CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
+CPUFLAGS += -DPROTECTED_MODE_STARTUP
 # If you enable FIXED_AND_VARIABLE it never makes it to the kernel!
 # you have to only enable variable. 
 CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
 CPUFLAGS += -DRAMTEST
+CPUFLAGS += -DUSE_DOC_MIL
 # This makes it fail sooner ...
 #CPUFLAGS += -DINBUF_COPY
 CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
@@ -32,7 +34,7 @@ OBJECTS += microcode.o
 OBJECTS += keyboard.o
 LINUX=$(TOP)/../linux-2.4.0-test6.sis/
 
-LINK = ld -T $(TOP)/src/mainboard/asus/cua/ldscript.ld -o $@ $(OBJECTS)
+LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
 CC=cc $(CFLAGS)
 CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
 

romimages/RON_ASUS_CUA/ldscript.ld

@@ -0,0 +1,114 @@
+/*
+ * Bootstrap code for the STPC Consumer
+ * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
+ *
+ * $Id$
+ *
+ */
+/* oh, barf. This won't work if all you use is .o's.  -- RGM */
+
+/*
+ *	Written by Johan Rydberg, based on work by Daniel Kahlin.
+ */
+/*
+ *	We use ELF as output format. So that we can
+ *	debug the code in some form. 
+ */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+
+/*
+ *	Memory map:
+ *
+ *	0x00000	(4*4096 bytes)	: stack
+ *	0x04000	(4096 bytes)	: private data 
+ *	0x05000			: data space
+ *	0x90000			: kernel stack
+ *	0xf0000	(64 Kbyte)	: EPROM
+ */
+MEMORY
+{
+	ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M	/* 128 MB memory is max for STPC */
+	rom (rx)  : ORIGIN = 0x000f0000, LENGTH = 128K	/* 128 K EPROM */
+}
+
+_PDATABASE	= 0x04000;
+_RAMBASE	= 0x05000;
+_KERNSTK	= 0x90000;
+
+/* should be parameterized but is not, yuck! */
+_ROMBASE	= 0x80000;
+
+/*
+ *	Entry point is not really nececary, since the mkrom(8)
+ *	tool creates a entry point that jumps to $0xc000:0x0000.
+ */
+/* baloney, but ... RGM*/
+ENTRY(_start)
+
+SECTIONS
+{
+	/*
+	 * First we place the code and read only data (typically const declared).
+	 * This get placed in rom.
+	 */
+	.text _ROMBASE : {
+		_text = .;
+		*(.text);
+		*(.rodata);
+		_etext = .;
+	}
+
+	_pdata = .;
+
+/*
+	.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +  
+					SIZEOF(.rodata)) {
+ */
+	.pdata _PDATABASE : AT ( _etext ) {
+		*(.pdata);
+	}
+
+	_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
+
+	/*
+	 * After the code we place initialized data (typically initialized
+	 * global variables). This gets copied into ram by startup code.
+	 * __data_start and __data_end shows where in ram this should be placed,
+	 * whereas __data_loadstart and __data_loadend shows where in rom to
+	 * copy from.
+	 */
+	.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
+		_data = .;
+		*(.data)
+		*(.sdata)
+		*(.sdata2)
+		*(.got)
+		_edata = .;
+	}
+    
+	_ldata	= LOADADDR(.data);
+	_eldata	= LOADADDR(.data) + SIZEOF(.data);
+ 	
+	/*
+	 * bss does not contain data, it is just a space that should be zero
+	 * initialized on startup. (typically uninitialized global variables)
+	 * crt0.S fills between __bss_start and __bss_end with zeroes.
+	 */
+	.bss ( ADDR(.data) + SIZEOF(.data) ) : {
+		_bss = .;
+		*(.bss)
+		*(.sbss)
+		*(COMMON)
+		_ebss = .;
+		_heap = .;
+	}
+}
+
+/*
+ *	This provides the start and end address for the whole image 
+ */
+_image	= LOADADDR(.text);
+_eimage	= LOADADDR(.data) + SIZEOF(.data);
+
+/* EOF */

src/northbridge/acer/m1631/chipset_init.inc

@@ -1,6 +1,6 @@
 /* SPD ram init */
 #define PM_DEVFN  CONFIG_ADDR(0, 0, 0)
-jmp chipsetinit_start
+jmpl chipsetinit_start
 /* table of settings for initial registers */
 /* format is register #, and value, OR value */
 register_table: 

src/northbridge/acer/m1631/ipl.S

@@ -17,13 +17,14 @@
  * ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
  * set the right value. 
  */
-#define INIT_MCR $0xf6641000
+#define INIT_MCR $0xf6621000
 #define WRITE_MCR0 movl %ecx, %eax ;  outl %eax, %dx
 /*#include <cpu/p5/start32.inc>*/
 .org 0xfe000
 .code16
 _start:	jmp _realstart
 gdt:	 //GDT entry 0 (null segment)
+	.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
 	.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
 	// GDT 1
 	.word	0xffff, 0x0000		/* flat code segment */
@@ -33,7 +34,7 @@ gdt:	 //GDT entry 0 (null segment)
 	.byte	0x0, 0x92, 0xcf, 0x0	
 
 gdtptr:
-	.word	3*8-1
+	.word	4*8-1
 	.long	gdt		/* we know the offset */
 	.long 0
 
@@ -55,13 +56,16 @@ _realstart:
 
 	/* invalidate the cache */
 	invd
-	data32	ljmp	$0x8, $.Lprotected
+	data32	ljmp	$0x10, $.Lprotected
 
 .Lprotected:
 	.code32
-	movw	$0x10, %bx
+	movw	$0x18, %bx
 	movw	%bx, %es
 	movw	%bx, %ds
+	movw	%bx, %es
+	movw	%bx, %fs
+	movw	%bx, %gs
 	movw	%bx, %ss
 #ifdef USE_BIG_REAL
 	andb	$0xfe, %al
@@ -73,7 +77,8 @@ code16
 
 /* make the flash writeable */
 /* select the south bridge, register 44 (base) */
-	movl	$0x80000044, %eax
+/* south bridge is device 7. 7 << 3 is 0x38 */
+	movl	$0x80003844, %eax
 	mov	$0x0cf8,%dx
 	outl	%eax,%dx
 /* but 0x40 makes flash writeable. You need this for DoC */
@@ -90,6 +95,7 @@ code16
 	CALLSP(pci_read_dword)*/
 	movb	$0xfc, %dl
 	inl	%dx, %eax
+	movl	%eax, %ecx
 	andl    $0xfffc, %ecx
 	orl	INIT_MCR,  %ecx
 	WRITE_MCR0
@@ -98,6 +104,10 @@ code16
 	CALLSP(pci_write_dword)
 	*/
 	rorl	$16, %ecx
+	/* clear out the CAS, since we assume start at zero
+	 * and increment 
+	 */
+	andb	$0xf0, %cl
 	/* test 8 bit CAS */
 	movb	$0, 0
 	movb	$1, 0x800
@@ -125,18 +135,25 @@ sizeram:
 	*/
 /* size is now in cx[19:16] */
 /* now size the dram */
-/* you had best have at least 32M; that's as small as we go */
+/* you had best have at least 4M; that's as small as we go */
 /* rorr 20 the ecx value, to get row size into lsb */
 	movb	$0, 0
 	ror	$20, %ecx
+	/* clear the size out to 4 MB */
+	andb	$0xf8, %cl
+	/* 4 MB */
 	movl	$0x400000, %esi
 1:
 #ifdef USE_BIG_REAL
 	addr32 	movb	$4, %es:(%esi)
 #else
+	/* move a 4 to the next power-of-two address. 
+	 * if there is no memory there, it will wrap to zero 
+	 */
  	movb	$4, %es:(%esi)
 #endif
-	cmpb	$4, 0
+	cmpb	$0, 0
+	/* if there is not a 0 at 0, the last write wrapped. Hop out */
 	jne	1f
 	inc	%cl
 	rol	$1, %esi
@@ -168,6 +185,12 @@ sizeram:
 	/* clear 4 banks */
 	andb	$0xfe, %cl
 	WRITE_MCR0
+	movl	$0x8000007c, %eax
+	movb	$0xf8, %dl
+	outl	%eax, %dx
+	movl	$0x2423c411, %eax
+	movb	$0xfc, %dl
+	outl	%eax, %dx
 	/*
 	mov	$0x6c, %al
 	CALLSP(pci_write_dword)
@@ -209,8 +232,8 @@ sizeram:
  * $Id$
  */
 #define DOC_WIN_SEG		0xfe00
-#define DOC_STACK_SEG		0x0400
+#define DOC_STACK		0x04000
-#define SPL_RAM_SEG		0x8000
+#define SPL_RAM		0x80000
 
 #define DOC_SPL_START_BLK	2	/* 0,1 for IPL */
 #define DOC_SPL_SIZE_IN_PAGE	126     /* 1 page = 512 bytes, total 63kB */
@@ -223,14 +246,14 @@ ipl_start:
 	movw	%ax, %ss
 	movw	$SPL_RAM_SEG, %ax
 	movw	%ax, %es
-	xorl	%sp, %sp			# clear %sp
+	movl	$DOC_STACK_SEG, %esp			# set %sp
 #endif
 	/* NOTE: in ollie's original code, %ds was at 0xfe00, i.e. 
 	 * 0xfe000, i.e. base of DoC. We have to adjust for that when 
 	 * we set %edi and %esi
 	 */
-	movl	$0x4000, %esp			# set %sp
+	movl	$DOC_STACK, %esp		# set %sp
-	xorl	%edx, %edx			# clear %dx, start of RAM
+	movl	$SPL_RAM, %edx			# start of RAM
 	xorl	%ecx, %ecx			# clear %ecx
 	movl	$0xfe800, %esi			# point %si to CDSN Data area
 	movl	$0xff000, %edi			# point %di to CDSN Control area
@@ -291,7 +314,10 @@ doc_delay:
 	jl	read_next_page			# no, read next page
 
 sis630ipl_end:
-	jmp	spl_vector			# jump to SPL vector
+	# jmp to 8000:0000, where SPL
+	# (LinuxBIOS) starts in RAM
+#	ljmp $0x10,$0x8000
+	jmp	spl_vector
 
 doc_reset:
         /* Input: AL = value write to DOC_CONTROL register
@@ -336,9 +362,11 @@ pci_read_dword:
 reset_vector:
 	.byte	0xea				# jmp to fe00:0000, where IPL
 	.word	0x0000, DOC_WIN_SEG		# starts in DoC
-
+.code32
 spl_vector:
-	.byte	0xea				# jmp to 8000:0000, where SPL
+	invd
-	.word	0x0000, SPL_RAM_SEG		# (LinuxBIOS) starts in RAM
+	jmpl	$0x10, $0x80000
-pad: 	.byte 0, 0, 0, 0, 0, 0
+# jmpl	$0x80000
+# put this here to buy some room!
+pad: 	.byte 0,0