mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Fixes for various acer stuff. Also, you can now #ifdef out the real-mode stuff
in start32.inc.
This commit is contained in:
Ronald G. Minnich
parent
b3b5a38f5f
commit
13275b3fea
4 changed files with 164 additions and 20 deletions
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@ -5,10 +5,12 @@ CPUFLAGS += -DINTEL_PPRO_MTRR
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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CPUFLAGS += -DPROTECTED_MODE_STARTUP
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# If you enable FIXED_AND_VARIABLE it never makes it to the kernel!
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# you have to only enable variable.
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CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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CPUFLAGS += -DRAMTEST
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CPUFLAGS += -DUSE_DOC_MIL
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# This makes it fail sooner ...
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#CPUFLAGS += -DINBUF_COPY
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
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@ -32,7 +34,7 @@ OBJECTS += microcode.o
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OBJECTS += keyboard.o
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LINUX=$(TOP)/../linux-2.4.0-test6.sis/
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LINK = ld -T $(TOP)/src/mainboard/asus/cua/ldscript.ld -o $@ $(OBJECTS)
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LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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114
romimages/RON_ASUS_CUA/ldscript.ld
Normal file
114
romimages/RON_ASUS_CUA/ldscript.ld
Normal file
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@ -0,0 +1,114 @@
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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* $Id$
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*
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*/
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/* oh, barf. This won't work if all you use is .o's. -- RGM */
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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* Memory map:
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*
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* 0x00000 (4*4096 bytes) : stack
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* 0x04000 (4096 bytes) : private data
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* 0x05000 : data space
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* 0x90000 : kernel stack
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* 0xf0000 (64 Kbyte) : EPROM
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*/
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MEMORY
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{
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ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is max for STPC */
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rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
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}
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_PDATABASE = 0x04000;
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_RAMBASE = 0x05000;
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_KERNSTK = 0x90000;
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/* should be parameterized but is not, yuck! */
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_ROMBASE = 0x80000;
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/*
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* Entry point is not really nececary, since the mkrom(8)
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* tool creates a entry point that jumps to $0xc000:0x0000.
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*/
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/* baloney, but ... RGM*/
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ENTRY(_start)
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SECTIONS
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{
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text _ROMBASE : {
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_text = .;
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*(.text);
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*(.rodata);
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_etext = .;
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}
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_pdata = .;
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/*
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.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
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SIZEOF(.rodata)) {
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*/
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.pdata _PDATABASE : AT ( _etext ) {
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*(.pdata);
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}
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_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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*(.got)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between __bss_start and __bss_end with zeroes.
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*/
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.bss ( ADDR(.data) + SIZEOF(.data) ) : {
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_bss = .;
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*(.bss)
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*(.sbss)
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*(COMMON)
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_ebss = .;
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_heap = .;
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}
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}
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/*
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* This provides the start and end address for the whole image
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*/
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_image = LOADADDR(.text);
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_eimage = LOADADDR(.data) + SIZEOF(.data);
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/* EOF */
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@ -1,6 +1,6 @@
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/* SPD ram init */
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#define PM_DEVFN CONFIG_ADDR(0, 0, 0)
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jmp chipsetinit_start
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jmpl chipsetinit_start
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/* table of settings for initial registers */
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/* format is register #, and value, OR value */
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register_table:
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@ -106,4 +106,4 @@ chipsetinit_start:
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inc %esi
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jmp 1b
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done_chipset_init:
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done_chipset_init:
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@ -17,13 +17,14 @@
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* set the right value.
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*/
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#define INIT_MCR $0xf6641000
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#define INIT_MCR $0xf6621000
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#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.code16
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_start: jmp _realstart
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gdt: //GDT entry 0 (null segment)
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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.byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
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// GDT 1
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.word 0xffff, 0x0000 /* flat code segment */
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@ -33,7 +34,7 @@ gdt: //GDT entry 0 (null segment)
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.byte 0x0, 0x92, 0xcf, 0x0
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gdtptr:
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.word 3*8-1
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.word 4*8-1
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.long gdt /* we know the offset */
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.long 0
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@ -55,13 +56,16 @@ _realstart:
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/* invalidate the cache */
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invd
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data32 ljmp $0x8, $.Lprotected
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data32 ljmp $0x10, $.Lprotected
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.Lprotected:
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.code32
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movw $0x10, %bx
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movw $0x18, %bx
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movw %bx, %es
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movw %bx, %ds
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movw %bx, %es
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movw %bx, %fs
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movw %bx, %gs
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movw %bx, %ss
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#ifdef USE_BIG_REAL
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andb $0xfe, %al
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@ -73,7 +77,8 @@ code16
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/* make the flash writeable */
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/* select the south bridge, register 44 (base) */
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movl $0x80000044, %eax
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/* south bridge is device 7. 7 << 3 is 0x38 */
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movl $0x80003844, %eax
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mov $0x0cf8,%dx
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outl %eax,%dx
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/* but 0x40 makes flash writeable. You need this for DoC */
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@ -90,6 +95,7 @@ code16
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CALLSP(pci_read_dword)*/
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movb $0xfc, %dl
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inl %dx, %eax
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movl %eax, %ecx
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andl $0xfffc, %ecx
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orl INIT_MCR, %ecx
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WRITE_MCR0
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@ -98,6 +104,10 @@ code16
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CALLSP(pci_write_dword)
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*/
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rorl $16, %ecx
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/* clear out the CAS, since we assume start at zero
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* and increment
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*/
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andb $0xf0, %cl
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/* test 8 bit CAS */
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movb $0, 0
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movb $1, 0x800
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@ -125,18 +135,25 @@ sizeram:
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*/
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/* size is now in cx[19:16] */
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/* now size the dram */
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/* you had best have at least 32M; that's as small as we go */
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/* you had best have at least 4M; that's as small as we go */
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/* rorr 20 the ecx value, to get row size into lsb */
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movb $0, 0
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ror $20, %ecx
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/* clear the size out to 4 MB */
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andb $0xf8, %cl
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/* 4 MB */
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movl $0x400000, %esi
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1:
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#ifdef USE_BIG_REAL
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addr32 movb $4, %es:(%esi)
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#else
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/* move a 4 to the next power-of-two address.
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* if there is no memory there, it will wrap to zero
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*/
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movb $4, %es:(%esi)
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#endif
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cmpb $4, 0
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cmpb $0, 0
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/* if there is not a 0 at 0, the last write wrapped. Hop out */
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jne 1f
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inc %cl
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rol $1, %esi
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@ -168,6 +185,12 @@ sizeram:
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/* clear 4 banks */
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andb $0xfe, %cl
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WRITE_MCR0
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movl $0x8000007c, %eax
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movb $0xf8, %dl
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outl %eax, %dx
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movl $0x2423c411, %eax
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movb $0xfc, %dl
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outl %eax, %dx
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/*
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mov $0x6c, %al
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CALLSP(pci_write_dword)
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@ -209,8 +232,8 @@ sizeram:
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* $Id$
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*/
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#define DOC_WIN_SEG 0xfe00
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#define DOC_STACK_SEG 0x0400
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#define SPL_RAM_SEG 0x8000
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#define DOC_STACK 0x04000
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#define SPL_RAM 0x80000
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#define DOC_SPL_START_BLK 2 /* 0,1 for IPL */
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#define DOC_SPL_SIZE_IN_PAGE 126 /* 1 page = 512 bytes, total 63kB */
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@ -223,14 +246,14 @@ ipl_start:
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movw %ax, %ss
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movw $SPL_RAM_SEG, %ax
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movw %ax, %es
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xorl %sp, %sp # clear %sp
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movl $DOC_STACK_SEG, %esp # set %sp
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#endif
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/* NOTE: in ollie's original code, %ds was at 0xfe00, i.e.
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* 0xfe000, i.e. base of DoC. We have to adjust for that when
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* we set %edi and %esi
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*/
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movl $0x4000, %esp # set %sp
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xorl %edx, %edx # clear %dx, start of RAM
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movl $DOC_STACK, %esp # set %sp
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movl $SPL_RAM, %edx # start of RAM
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xorl %ecx, %ecx # clear %ecx
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movl $0xfe800, %esi # point %si to CDSN Data area
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movl $0xff000, %edi # point %di to CDSN Control area
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@ -291,7 +314,10 @@ doc_delay:
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jl read_next_page # no, read next page
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sis630ipl_end:
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jmp spl_vector # jump to SPL vector
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# jmp to 8000:0000, where SPL
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# (LinuxBIOS) starts in RAM
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# ljmp $0x10,$0x8000
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jmp spl_vector
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doc_reset:
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/* Input: AL = value write to DOC_CONTROL register
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@ -336,9 +362,11 @@ pci_read_dword:
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reset_vector:
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.byte 0xea # jmp to fe00:0000, where IPL
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.word 0x0000, DOC_WIN_SEG # starts in DoC
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.code32
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spl_vector:
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.byte 0xea # jmp to 8000:0000, where SPL
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.word 0x0000, SPL_RAM_SEG # (LinuxBIOS) starts in RAM
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pad: .byte 0, 0, 0, 0, 0, 0
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invd
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jmpl $0x10, $0x80000
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# jmpl $0x80000
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# put this here to buy some room!
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pad: .byte 0,0
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