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mainboard/intel/amenia: Configure DDI0, DDI1 HPD GPIO lines.

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1. Configure GPIO_199 and GPIO_200 as NF2 to work as HPD.
2. Make 20k Pullup and remove duplicate code.

Change-Id: I8c78d867b03d5f2a6f02165c20777ae25e352ce7
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14899
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Abhay Kumar 2016-05-18 18:29:12 -07:00 • committed by Martin Roth
parent 988b3fd2ee
commit 1285598a99
1 changed files with 3 additions and 6 deletions
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9
src/mainboard/intel/amenia/mainboard.c
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@ -114,9 +114,6 @@ static const struct pad_config amenia_gpios[] = {
PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */
PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */
PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */
PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */
PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */
@ -129,9 +126,9 @@ static const struct pad_config amenia_gpios[] = {
PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */
PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */
PAD_CFG_NF(GPIO_199,NATIVE,DEEP,NF2), /* HV_DDI1_HPD */
PAD_CFG_NF(GPIO_200,NATIVE,DEEP,NF2), /* HV_DDI0_HPD */
PAD_CFG_NF(PMC_SPI_FS1,NATIVE,DEEP,NF2), /* HV_DDI2_HPD */
PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */
PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */
PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */
};