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missing file.
This commit is contained in:
Ronald G. Minnich
parent
02846565a9
commit
11c8c6f387
1 changed files with 542 additions and 0 deletions
542
src/mainboard/via/epia-m/smbus.inc
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542
src/mainboard/via/epia-m/smbus.inc
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/* Useful macros PCIBUS, and SMBUS functions for getting DRAM going. */
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/* courtesy Eric Biederman of linuxnetworx.com */
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#define CS_WRITE_BYTE(addr, byte) \
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movl $addr, %eax ; \
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movl $byte, %edx ; \
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PCI_WRITE_CONFIG_BYTE
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#define CS_WRITE_WORD(addr, word) \
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movl $addr, %eax ; \
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movl $word, %ecx ; \
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PCI_WRITE_CONFIG_WORD
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#define CS_WRITE_LONG(addr, dword) \
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movl $addr, %eax ; \
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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#define DEVFN(device, function) (((device) << 3) + (function))
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#ifndef CONFIG_ADDR
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#endif
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/* jump around these subrs */
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jmp smbus_pcibus_end
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/* generic SMB routines that work for many systems. The only one that might
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* not work is the enable_smbus.
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* you have to define PM_FUNCTION for this to work.
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*/#define SMBUS_IO_BASE 0xf00
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#define SMBHSTSTAT 0
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#define SMBHSTCTL 2
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#define SMBHSTCMD 3
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#define SMBHSTADD 4
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#define SMBHSTDAT0 5
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#define SMBHSTDAT1 6
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#define SMBBLKDAT 7
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/* (DA) Lines added to get this to compile */
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#define PM_DEVFN CONFIG_ADDR(0,0x11*8,0)
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#define DRAM_CONFIG_PORT 0x5a
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#define SMBUS_MEM_DEVICE_0 0x50
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#define LAST_SMBUS_MEM_DEVICE SMBUS_MEM_DEVICE_0
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#define REGISTERED_DRAM_REGISTER $0x69
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#define REGISTERED_DRAM $0x2d
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#define NONREGISTERED_DRAM $0
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enable_smbus:
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/* put the SMBUS at port 0xf00 */
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CS_WRITE_WORD(PM_DEVFN+ 0xd0, SMBUS_IO_BASE|1) /* iobase addr */
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CS_WRITE_BYTE(PM_DEVFN + 0xd2, (0x4 << 1) | 1) /* smbus enable */
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CS_WRITE_WORD(PM_DEVFN + 0x4, 1) /* iospace enable */
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RET_LABEL(enable_smbus)
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/*
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* Routine: setup_smbus
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* Arguments: none
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* Results: none
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* Trashed: eax, edx
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* Effects: The smbus is enabled
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*/
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setup_smbus:
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xor %eax,%eax
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movl $(SMBUS_IO_BASE +SMBHSTSTAT), %edx
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outb %al, %dx
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RET_LABEL(setup_smbus)
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#ifndef SMBUS_MEM_DEVICE_0
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#define SMBUS_MEM_DEVICE_0 (0xa << 3)
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#endif
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#define SMBUS_MEM_DEVICE_1 (SMBUS_MEM_DEVICE_0 +1)
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#define SMBUS_MEM_DEVICE_2 (SMBUS_MEM_DEVICE_0 +2)
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#define SMBUS_MEM_DEVICE_3 (SMBUS_MEM_DEVICE_0 +3)
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/*
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* Routine: smbus_wait_until_ready
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* Arguments: none
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* Results: none
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* Trashed: eax, edx
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* Effects: Upon return the smbus is ready to accept commands
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*/
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smbus_wait_until_ready:
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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1: inb %dx, %al
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testb $1, %al
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jnz 1b
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RET_LABEL(smbus_wait_until_ready)
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/*
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* Routine: smbus_wait_until_done
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* Arguments: none
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* Results: none
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* Trashed: eax, edx
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* Effects: Upon return the smbus has completed it's most recent transation
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*/
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smbus_wait_until_done:
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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1: inb %dx, %al
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testb $1, %al
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jnz 1b
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2: testb $0xFE, %al
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jnz 3f
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inb %dx, %al
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testb $0xFE, %al
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jz 2b
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3: RET_LABEL(smbus_wait_until_done)
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/*
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* Routine: smbus_read_byte
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* Arguments: %esp return address
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* %bl device on the smbus to read from
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* %bh address on the smbus to read
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*
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* Results: zf clear
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* byte read %eax
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* On Error:
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* zf set
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* %eax trashed
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*
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* Trashed: %edx, %eax
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* Effects: reads a byte off of the smbus
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*/
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#define SMBUS_READ_BYTE(device, address) \
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movl $( (device) | ((address) << 8)), %ebx ; \
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CALLSP(smbus_read_byte)
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smbus_read_byte:
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/* poll until the smbus is ready for commands */
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CALL_LABEL(smbus_wait_until_ready)
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/* clear any lingering errors, so that the transaction will run */
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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inb %dx, %al
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outb %al, %dx
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/* set the device I'm talking to */
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movl $(SMBUS_IO_BASE + SMBHSTADD), %edx
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movb %bl /* device */, %al
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shlb $1, %al
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orb $1, %al
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outb %al, %dx
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/* set the command address... */
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movl $(SMBUS_IO_BASE + SMBHSTCMD), %edx
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movb %bh /* address */, %al
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outb %al, %dx
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/* clear the data byte */
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movl $(SMBUS_IO_BASE + SMBHSTDAT0), %edx
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xorl %eax, %eax
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outb %al, %dx
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/* start a byte read, with interrupts disabled */
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movl $(SMBUS_IO_BASE + SMBHSTCTL), %edx
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movl $((0x2 << 2) | (1 << 6)), %eax
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outb %al, %dx
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/* poll for transaction completion */
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CALL_LABEL(smbus_wait_until_done)
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/* read the results and see if we succeded */
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movl $(SMBUS_IO_BASE + SMBHSTSTAT), %edx
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inb %dx, %al
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testb $0x02, %al
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jz 1f
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movl $(SMBUS_IO_BASE + SMBHSTDAT0), %edx
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inb %dx, %al
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1:
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RETSP
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#if 1 // TEMPORARY (DA) 20030718
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/* now for code to actually do the deed. Eric did such a good job that
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* this stuff is basically generic.
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*/
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/*
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* Routine: spd_set_drb
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* Arguments: None
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*
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* Trashed: %eax, %ebx, %ecx, %edx, %esi, %edi, %ebp, %esp, %eflags
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* Effects: Uses serial presence detect to set the
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* DRB registers which holds the ending memory address assigned
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* to each DIMM.
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* Notes: %ebp holds the currently detected end of memory.
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* %ebx holds the configuration port & SMBUS_MEM_DEVICE for
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* the current iteration through the loop.
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* %edi holds the memory size for the first side of the DIMM.
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* %esi holds the memory size for the second side of the DIMM.
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* memory size is represent as a power of 2.
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* An unset memory size is represented as -1 ie. 0xFFFFFFFF
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*/
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spd_set_drb:
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xorl %ebp, %ebp /* clear the memory address */
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movl $((DRAM_CONFIG_PORT << 16) |SMBUS_MEM_DEVICE_0), %ebx
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spd_set_drb_loop_top:
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// set -1 power-of-two for side 1 (called bank0 in most chipset docs)
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xorl %edi, %edi
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subl $1, %edi
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// set -1 power-of-two for side 2 (called bank1 in most chipset docs)
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xorl %esi, %esi
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subl $1, %esi
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movb $3, %bh /* rows */
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CALLSP(smbus_read_byte)
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// If it's zero, then we just set current %ebp into the row
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// end register
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jz 20f
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andl $0xf, %eax
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addl %eax, %edi
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movb $4, %bh /* columns */
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CALLSP(smbus_read_byte)
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andl $0xf, %eax
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addl %eax, %edi
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movb $17, %bh /* banks */
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CALLSP(smbus_read_byte)
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andl $0xff, %eax
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bsrl %eax, %ecx
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addl %ecx, %edi
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/* Get the module data width and convert it to a power of two */
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movb $7, %bh /* (high byte) */
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CALLSP(smbus_read_byte)
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andl $0xff, %eax
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movl %eax, %ecx
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shll $8, %ecx
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movb $6, %bh /* (low byte) */
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CALLSP(smbus_read_byte)
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andl $0xff, %eax
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orl %eax, %ecx
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bsrl %ecx, %eax
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addl %eax, %edi
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/* now I have the ram size in bits as a power of two (less 1) */
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// It is less 1 since we started with -1 above.
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// OK, BITS as power of two (but minus 1)
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// So, e.g., 8 MB is 64 Mb, 64 Mb is 26 bits. Subtract
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// (26-1) or 25
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subl $25, %edi /* Make it multiples of 8MB */
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/* side two */
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movb $5, %bh /* number of physical banks */
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CALLSP(smbus_read_byte)
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cmp $1, %al
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// it's only one bank
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jbe 20f
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// It's two banks. So assign edi to esi
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/* for now only handle the symmetrical case */
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// it's two banks, assume however that they're the same size.
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// it's stupid to have any other kind, right?
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movl %edi, %esi
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20:
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/* Compute the end address for the DRB register */
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// If it is >= 8, i.e. >= 2^8 or 256, skip it.
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// >= 8 is a bogus value.
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cmpl $8, %edi
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jae 21f
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movl $1, %eax
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movl %edi, %ecx
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shll %cl, %eax
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// increment row-end by the size of this DIMM half
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addl %eax, %ebp
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21:
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/* Write the comuputed value for the first half of the DIMM */
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movl %ebp, %edx /* value to write into %edx */
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movl %ebx, %eax
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shrl $16, %eax /* port address into %eax */
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PCI_WRITE_CONFIG_BYTE
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/* Compute the end address for the DRB register */
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cmpl $8, %esi
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jae 30f
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mov $1, %eax
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movl %esi, %ecx
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shll %cl, %eax
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addl %eax, %ebp
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30:
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/* Write the comuputed value for the second half of the DIMM */
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movl %ebp, %edx /* value to write into %edx */
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movl %ebx, %eax
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shrl $16, %eax /* port address into %eax */
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addl $1, %eax /* The second half uses one port high */
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PCI_WRITE_CONFIG_BYTE
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addl $0x00020001, %ebx /* increment the smbus device & the config port */
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cmpb $LAST_SMBUS_MEM_DEVICE, %bl /* see if I have reached the end */
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jbe spd_set_drb_loop_top
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/* o.k. I'm done return now */
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RET_LABEL(spd_set_drb)
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/*
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* Routine: spd_set_dramc
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* Arguments: None
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*
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* Trashed: %eax, %ebx, %edx, %esp, %eflags
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* Effects: Uses serial presence detect to set the
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* DRAMC register, which records if ram is registerd or not,
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* and controls the refresh rate.
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* The refresh rate is not set here, as memory refresh
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* cannot be enbaled until after memory is initialized.
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* see spd_enable_refresh.
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* Notes:
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* FIXME: Check for illegal/unsupported ram configurations and abort
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* FIXME: won't work with non-contiguous DRAM size regs (like VIA)
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* need an indirect pointer to an array of reg #s
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*/
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spd_set_dramc:
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/* auto detect if ram is registered or not. */
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/* The DRAMC register also contorls the refresh rate but we can't
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* set that here because we must leave refresh disabled.
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* see: spd_enable_refresh
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*/
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/* Find the first dimm and assume the rest are the same */
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/* Load the smbus device and port int %ebx */
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movl $((21 << 8) | SMBUS_MEM_DEVICE_0), %ebx
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1: CALLSP(smbus_read_byte)
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jz 2f
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andl $0x12, %eax
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jmp spd_set_dramc_out
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2: addl $1, %ebx /* increment the device */
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cmpb $LAST_SMBUS_MEM_DEVICE, %bl
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jbe 1b
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/* We couldn't find anything we must have no memory */
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jmp no_memory
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spd_set_dramc_out:
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testb $0x12, %al
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jz 2f
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movl REGISTERED_DRAM, %eax
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jmp 1f
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2: movl NONREGISTERED_DRAM, %eax
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1: movl %eax, %edx
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movl REGISTERED_DRAM_REGISTER, %eax
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PCI_WRITE_CONFIG_BYTE
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RET_LABEL(spd_set_dramc)
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/*
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* Routine: spd_read_refresh
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* Arguments: None
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*
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* Trashed: %eax, %ebx, %ecx, %edx, %esp, %eflags
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* Effects: Uses serial presence detect to find refresh rates.
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* returns the rate in %eax
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* It's up to you to set hardware up.
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* FIXME: Check for illegal/unsupported ram configurations and abort
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*/
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spd_read_refresh:
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/* Find the first dimm and assume the rest are the same */
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/* Load the smbus device and port int %ebx */
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movl $((12 << 8) | SMBUS_MEM_DEVICE_0), %ebx
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1: CALLSP(smbus_read_byte)
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jz 2f
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andl $0x7f, %eax
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jmp spd_enable_refresh_out
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2: addl $1, %ebx /* increment the device */
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cmpb $LAST_SMBUS_MEM_DEVICE, %bl
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jbe 1b
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/* We couldn't find anything we must have no memory */
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xorl %eax, %eax
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spd_enable_refresh_out:
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RET_LABEL(spd_enable_refresh)
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/*
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* Routine: spd_set_rps
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* Arguments: None
|
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*
|
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* Trashed: %eax, %ebx, %ecx, %edx, %esi, %edi, %esp, %eflags
|
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* Effects: Uses serial presence detect to set the row size
|
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* on a given DIMM
|
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* Notes: %esi accumulates the row sizes of all of the DIMMs
|
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* %ecx holds the current bit into into %esi
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* %bl holds the current SMBUS device
|
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* FIXME: Check for illegal/unsupported ram configurations and abort
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*/
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spd_set_rps:
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/* The RPS register holds the size of a ``page'' of DRAM on each DIMM */
|
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/* default all page sizes to 2KB */
|
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xorl %esi, %esi
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/* Index into %esi of bit to set */
|
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movl $0 , %ecx
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/* Load the smbus device into %ebx */
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movl $SMBUS_MEM_DEVICE_0, %ebx
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1: movb $3, %bh
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CALLSP(smbus_read_byte) /* row address bits */
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jz 2f
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andl $0xf, %eax
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movl %eax, %edi
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/* I now have the row page size as a power of 2 */
|
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subl $11, %edi /* Now make it in multiples of 2Kb */
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jbe 2f
|
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/* FIXME: do something with page sizes greather than 8KB!! */
|
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shll %cl, %edi
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orl %edi, %esi
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/* side two */
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movb $5, %bh
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CALLSP(smbus_read_byte) /* number of physical banks */
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cmp $1, %al
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jbe 2f
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/* for now only handle the symmtrical case */
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shll $2, %edi
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shll %cl, %edi
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orl %edi, %esi
|
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|
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2: addl $1, %ebx /* increment the device */
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addl $4, %ecx /* increment the shift count */
|
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cmpb $LAST_SMBUS_MEM_DEVICE, %bl
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jbe 1b
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movl $0x7f, %eax
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/* I'm not sure what we should do here. Do nothing. */
|
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/* PCI_WRITE_CONFIG_WORD*/
|
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RET_LABEL(spd_set_rps)
|
||||
|
||||
/*
|
||||
* Routine: spd_set_pgpol
|
||||
* Arguments: None
|
||||
*
|
||||
* Trashed: %eax, %ebx, %ecx, %edx, %esi, %esp, %eflags
|
||||
* Effects: Uses serial presence detect to set the number of banks
|
||||
* on a given DIMM
|
||||
* Notes: %esi accumulates the banks sizes of all of the DIMMs
|
||||
* %ecx holds the current bit into into %esi
|
||||
* %bl holds the current SMBUS device
|
||||
* FIXME: Check for illegal/unsupported ram configurations and abort
|
||||
*/
|
||||
|
||||
spd_set_pgpol:
|
||||
/* The PGPOL register stores the number of logical banks per DIMM,
|
||||
* and number of clocks the DRAM controller waits in the idle
|
||||
* state.
|
||||
*/
|
||||
/* default all bank counts 2 */
|
||||
xorl %esi, %esi
|
||||
/* Index into %esi of bit to set */
|
||||
movl $0 , %ecx
|
||||
/* Load the smbus device into %ebx */
|
||||
movl $SMBUS_MEM_DEVICE_0, %ebx
|
||||
|
||||
1: movb $17, %bh
|
||||
CALLSP(smbus_read_byte) /* logical banks */
|
||||
jz 2f
|
||||
cmp $0x4, %eax
|
||||
jl 2f
|
||||
movl $0x1, %eax
|
||||
shll %cl, %eax
|
||||
orl %eax, %esi
|
||||
/* side two */
|
||||
movb $5, %bh
|
||||
CALLSP(smbus_read_byte) /* number of physical banks */
|
||||
cmp $1, %al
|
||||
jbe 2f
|
||||
/* for now only handle the symmtrical case */
|
||||
movl $0x2, %eax
|
||||
shll %cl, %eax
|
||||
orl %eax, %esi
|
||||
|
||||
2: addl $1, %ebx /* increment the device */
|
||||
addl $2, %ecx /* increment the shift count */
|
||||
cmpb $LAST_SMBUS_MEM_DEVICE, %bl
|
||||
jbe 1b
|
||||
|
||||
shll $8, %esi
|
||||
orl $0x7, %esi /* 32 clocks idle time */
|
||||
movl %esi, %ecx
|
||||
movl $0x78, %eax
|
||||
/* I'm unclear on the concept for non-intel devices */
|
||||
/* PCI_WRITE_CONFIG_WORD*/
|
||||
RET_LABEL(spd_set_pgpol)
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Routine: spd_enable_nbxcfg
|
||||
* Arguments: None
|
||||
*
|
||||
* Trashed: %eax, %ebx, %ecx, %edx, %esi, %esp, %eflags
|
||||
* Effects: Uses serial presence detect to set the
|
||||
* ECC support flags in the NBXCFG register
|
||||
* Notes: %esi accumulates the ECC support of the individual DIMMs.
|
||||
* %ecx holds the bit that should be flipped for the current DIMM.
|
||||
* %bl holds the smbus device that corresponds to the current DIMM.
|
||||
* FIXME: Check for illegal/unsupported ram configurations and abort
|
||||
*/
|
||||
|
||||
spd_set_nbxcfg:
|
||||
/* say all dimms have no ECC support */
|
||||
movl $0xFF, %esi
|
||||
/* Index into %esi of bit to set */
|
||||
movl $0 , %ecx
|
||||
/* Load the smbus device into %ebx */
|
||||
movl $SMBUS_MEM_DEVICE_0, %ebx
|
||||
|
||||
1: movb $11, %bh
|
||||
CALLSP(smbus_read_byte) /* module error correction type */
|
||||
jz 2f
|
||||
cmp $0x2, %eax /* 0 == None, 1 == Parity, 2 == ECC */
|
||||
jne 2f
|
||||
movl $0x1, %eax
|
||||
shll %cl, %eax
|
||||
xorl %eax, %esi
|
||||
|
||||
/* side two */
|
||||
movb $5, %bh
|
||||
CALLSP(smbus_read_byte) /* number of physical banks */
|
||||
cmp $1, %al
|
||||
jbe 2f
|
||||
/* The only is the symmtrical case */
|
||||
movl $0x2, %eax
|
||||
shll %cl, %eax
|
||||
xorl %eax, %esi
|
||||
|
||||
2: addl $1, %ebx /* increment the device */
|
||||
addl $2, %ecx /* increment the shift count */
|
||||
cmpb $LAST_SMBUS_MEM_DEVICE, %bl
|
||||
jbe 1b
|
||||
|
||||
movl %esi, %edx
|
||||
/* at some point, we need to indicate how to turn ECC on. Not yet.
|
||||
movl $0x53, %eax
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
*/
|
||||
RET_LABEL(spd_set_nbxcfg)
|
||||
|
||||
#endif
|
||||
|
||||
smbus_pcibus_end:
|
||||
Loading…
Add table
Reference in a new issue