mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
m57sli mostly builds again. The stage0 is too large at 24k.
We need to figure out if we should just grow stage0. My inclination is to say 'yes'. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@877 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
76167990ed
commit
11c6d0d98d
11 changed files with 76 additions and 67 deletions
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@ -300,9 +300,9 @@ void STOP_CAR_AND_CPU(void)
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#if MEM_TRAIN_SEQ == 1
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static inline void train_ram_on_node(unsigned nodeid, unsigned coreid,
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void train_ram_on_node(unsigned nodeid, unsigned coreid,
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struct sys_info *sysinfo,
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unsigned retcall);
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void * retcall);
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#endif
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/**
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@ -479,7 +479,7 @@ cpu_init_detectedx = 0;
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/* this is not done on Serengeti. */
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#if MEM_TRAIN_SEQ == 1
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train_ram_on_node(id.nodeid, id.coreid, sysinfo,
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STOP_CAR_AND_CPU);
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(void *)STOP_CAR_AND_CPU);
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#endif
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/* this is inline and there is no return. */
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STOP_CAR_AND_CPU();
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@ -43,3 +43,6 @@
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/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
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/* preferably by asking the CPU, not be a DEFINE! */
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#define CPU_ADDR_BITS 40
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/* you don't want to set this in Kconfig or dts either. It's dangerous! */
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#define CONFIG_AP_CODE_IN_CAR 0
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@ -26,6 +26,7 @@
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#include <macros.h>
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#include <spd.h>
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#include <cpu.h>
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#include <globalvars.h>
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#include <msr.h>
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#include <device/pci.h>
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#include <pci_ops.h>
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@ -1938,10 +1939,11 @@ out:
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#if MEM_TRAIN_SEQ > 0
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static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned int v)
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void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo)
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{
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int ii;
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int v = 1; /* used to be a parameter; consider making it one again */
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u64 tsc[4];
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@ -1972,9 +1974,8 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
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}
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tsc[1] = cycles();
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if (DQS_TRAIN_DEBUG) {
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printk(BIOS_DEBUG, "set DQS timing:DQSPos: ");
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printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x", i);
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}
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print_debug_hex8(i);
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}
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if(train_DqsPos(ctrl, sysinfo)) {
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@ -1987,9 +1988,8 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
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tsc[2] = cycles();
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if (DQS_TRAIN_DEBUG) {
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printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: ");
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printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
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}
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print_debug_hex8(i);
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}
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if(train_DqsRcvrEn(ctrl, 2, sysinfo)){
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sysinfo->mem_trained[i]=0x83; //
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@ -2011,7 +2011,7 @@ out:
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if(v) {
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for(ii=0;ii<4;ii++) {
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print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo);
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printk(BIOS_ERR, "Total DQS Training : tsc %d: %llx", ii, tsc[ii]);
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}
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}
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@ -2025,17 +2025,21 @@ out:
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#if MEM_TRAIN_SEQ == 1
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static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox)
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{
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dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy
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dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo); // keep the output tidy
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// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8);
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// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9);
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sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
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}
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static void copy_and_run_ap_code_in_car(unsigned ret_addr);
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static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
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void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, void * retcall)
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{
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if(coreid) return; // only do it on core0
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struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
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/* this is a little weird. We're going to get the address of the global vars. But we're in CAR, so
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* it's really private. We're going to copy from global memory, which is node 0 memory, which
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* is working at this point.
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*/
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struct sys_info *sysinfox = & global_vars()->sys_info;
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wait_till_sysinfo_in_ram(); // use pci to get it
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if(sysinfox->mem_trained[nodeid] == 0x80) {
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@ -2046,7 +2050,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
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sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
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memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
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#else
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memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
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memcpy(sysinfo, sysinfox, sizeof(*sysinfo));
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#endif
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set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
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#if CONFIG_AP_CODE_IN_CAR == 0
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@ -2056,7 +2060,9 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
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#else
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/* Can copy dqs_timing to ap cache and run from cache?
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* we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ?
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* not sure how we'll return.
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*/
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#warning resolve issues about returning from the copy_and_run_ap_code_in_car.
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copy_and_run_ap_code_in_car(retcall);
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// will go back by jump
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#endif
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@ -2653,10 +2653,10 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
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#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
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//We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some
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u32 basek_pri;
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u32 basek_pri = 0;
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for(i=0; i<controllers; i++) {
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u32 base;
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unsigned base_k;
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u32 base_k;
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base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3));
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if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
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continue;
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@ -41,7 +41,7 @@ static void ide_init(struct device *dev)
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u16 word;
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u8 byte;
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word = pci_conf1_read_config16(dev, 0x50);
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word = pci_read_config16(dev, 0x50);
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/* Ensure prefetch is disabled */
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word &= ~((1 << 15) | (1 << 13));
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if (conf->ide1_enable) {
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@ -56,15 +56,15 @@ static void ide_init(struct device *dev)
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word |= (1<<12);
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word |= (1<<14);
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pci_conf1_write_config16(dev, 0x50, word);
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pci_write_config16(dev, 0x50, word);
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byte = 0x20 ; // Latency: 64-->32
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pci_conf1_write_config8(dev, 0xd, byte);
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pci_write_config8(dev, 0xd, byte);
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dword = pci_conf1_read_config32(dev, 0xf8);
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dword = pci_read_config32(dev, 0xf8);
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dword |= 12;
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pci_conf1_write_config32(dev, 0xf8, dword);
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pci_write_config32(dev, 0xf8, dword);
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#ifdef CONFIG_PCI_ROM_RUN
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pci_dev_init(dev);
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#endif
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@ -144,10 +144,10 @@ static void lpc_common_init(struct device *dev, int master)
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u32 dword;
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/* IO APIC initialization */
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byte = pci_conf1_read_config8(dev, 0x74);
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byte = pci_read_config8(dev, 0x74);
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byte |= (1<<0); // enable APIC
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pci_conf1_write_config8(dev, 0x74, byte);
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dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
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pci_write_config8(dev, 0x74, byte);
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dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
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setup_ioapic(dword, master);
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}
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@ -162,8 +162,8 @@ static void enable_hpet(struct device *dev)
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{
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unsigned long hpet_address;
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pci_conf1_write_config32(dev,0x44, 0xfed00001);
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hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe;
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pci_write_config32(dev,0x44, 0xfed00001);
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hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
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printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
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}
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#endif
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@ -180,20 +180,20 @@ static void lpc_init(struct device *dev)
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#warning posted memory write enable disabled in mcp55 lpc?
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#if 0
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/* posted memory write enable */
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byte = pci_conf1_read_config8(dev, 0x46);
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pci_conf1_write_config8(dev, 0x46, byte | (1<<0));
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byte = pci_read_config8(dev, 0x46);
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pci_write_config8(dev, 0x46, byte | (1<<0));
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#endif
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/* power after power fail */
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#if 1
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on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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get_option(&on, "power_on_after_fail");
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byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE);
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byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
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byte &= ~0x40;
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if (!on) {
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byte |= 0x40;
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}
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pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte);
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pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
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printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
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#endif
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/* Throttle the CPU speed down for testing */
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@ -202,7 +202,7 @@ static void lpc_init(struct device *dev)
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if(on) {
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u16 pm10_bar;
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u32 dword;
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pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00);
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pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
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outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
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dword = inl(pm10_bar + 0x10);
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on = 8-on;
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@ -213,16 +213,16 @@ static void lpc_init(struct device *dev)
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#if 0
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// default is enabled
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/* Enable Port 92 fast reset */
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byte = pci_conf1_read_config8(dev, 0xe8);
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byte = pci_read_config8(dev, 0xe8);
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byte |= ~(1 << 3);
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pci_conf1_write_config8(dev, 0xe8, byte);
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pci_write_config8(dev, 0xe8, byte);
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#endif
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/* Enable Error reporting */
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/* Set up sync flood detected */
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byte = pci_conf1_read_config8(dev, 0x47);
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byte = pci_read_config8(dev, 0x47);
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byte |= (1 << 1);
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pci_conf1_write_config8(dev, 0x47, byte);
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pci_write_config8(dev, 0x47, byte);
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/* Set up NMI on errors */
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byte = inb(0x70); // RTC70
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@ -286,7 +286,7 @@ static void mcp55_lpc_enable_childrens_resources(struct device *dev)
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int i;
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int var_num = 0;
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reg = pci_conf1_read_config32(dev, 0xa0);
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reg = pci_read_config32(dev, 0xa0);
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for (link = 0; link < dev->links; link++) {
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struct device *child;
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@ -324,9 +324,9 @@ static void mcp55_lpc_enable_childrens_resources(struct device *dev)
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}
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}
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}
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pci_conf1_write_config32(dev, 0xa0, reg);
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pci_write_config32(dev, 0xa0, reg);
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for(i=0;i<var_num;i++) {
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pci_conf1_write_config32(dev, 0xa8 + i*4, reg_var[i]);
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pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
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}
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@ -52,7 +52,7 @@ static struct device *find_lpc_dev( struct device *dev, unsigned devfn)
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(lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
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) ) {
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u32 id;
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id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID);
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id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
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if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
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(id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
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) {
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@ -82,7 +82,7 @@ static void mcp55_enable(struct device *dev)
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/* sorry. Again, anonymous unions etc. would make this easier. */
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if(dev->id.pci.device==0x0000) {
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vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID);
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vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
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deviceid = (vendorid>>16) & 0xffff;
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// vendorid &= 0xffff;
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} else {
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@ -180,14 +180,14 @@ static void mcp55_enable(struct device *dev)
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if(!sm_dev) return;
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if ( sm_dev ) {
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reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
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reg_old = reg = pci_read_config32(sm_dev, 0xe4);
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if (!dev->enabled) { //disable it
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reg |= (1<<index2);
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}
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if (reg != reg_old) {
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pci_conf1_write_config32(sm_dev, 0xe4, reg);
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pci_write_config32(sm_dev, 0xe4, reg);
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}
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}
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@ -199,14 +199,14 @@ static void mcp55_enable(struct device *dev)
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if ( index == 0) { // for LPC
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// expose ioapic base
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byte = pci_conf1_read_config8(lpc_dev, 0x74);
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byte = pci_read_config8(lpc_dev, 0x74);
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byte |= ((1<<1)); // expose the BAR
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pci_conf1_write_config8(dev, 0x74, byte);
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pci_write_config8(dev, 0x74, byte);
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// expose trap base
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byte = pci_conf1_read_config8(lpc_dev, 0xdd);
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byte = pci_read_config8(lpc_dev, 0xdd);
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byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
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pci_conf1_write_config8(dev, 0xdd, byte);
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pci_write_config8(dev, 0xdd, byte);
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return;
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@ -216,16 +216,16 @@ static void mcp55_enable(struct device *dev)
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sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
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if(!sm_dev) return;
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final_reg = pci_conf1_read_config32(sm_dev, 0xe8);
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final_reg = pci_read_config32(sm_dev, 0xe8);
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final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
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pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
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pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first
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#if 0
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reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
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reg_old = reg = pci_read_config32(sm_dev, 0xe4);
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// reg |= (1<<0);
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reg &= ~(0x3f<<4);
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if (reg != reg_old) {
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printk_debug("mcp55.c pcie enabled\n");
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pci_conf1_write_config32(sm_dev, 0xe4, reg);
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pci_write_config32(sm_dev, 0xe4, reg);
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}
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#endif
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}
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@ -238,9 +238,9 @@ static void mcp55_enable(struct device *dev)
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if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
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sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
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if(!sm_dev) return;
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reg_old = pci_conf1_read_config32(sm_dev, 0xe8);
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reg_old = pci_read_config32(sm_dev, 0xe8);
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if (final_reg != reg_old) {
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pci_conf1_write_config32(sm_dev, 0xe8, final_reg);
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pci_write_config32(sm_dev, 0xe8, final_reg);
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}
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}
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@ -251,7 +251,7 @@ static void mcp55_enable(struct device *dev)
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void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
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unsigned int device)
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{
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pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
|
||||
pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -43,23 +43,23 @@ static void pci_init(struct device *dev)
|
|||
#endif
|
||||
|
||||
/* System error enable */
|
||||
dword = pci_conf1_read_config32(dev, 0x04);
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
dword |= (1<<8); /* System error enable */
|
||||
dword |= (1<<30); /* Clear possible errors */
|
||||
pci_conf1_write_config32(dev, 0x04, dword);
|
||||
pci_write_config32(dev, 0x04, dword);
|
||||
|
||||
#if 1
|
||||
//only need (a01,xx]
|
||||
word = pci_conf1_read_config16(dev, 0x48);
|
||||
word = pci_read_config16(dev, 0x48);
|
||||
word |= (1<<0); /* MRL2MRM */
|
||||
word |= (1<<2); /* MR2MRM */
|
||||
pci_conf1_write_config16(dev, 0x48, word);
|
||||
pci_write_config16(dev, 0x48, word);
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
dword = pci_conf1_read_config32(dev, 0x4c);
|
||||
dword = pci_read_config32(dev, 0x4c);
|
||||
dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
|
||||
pci_conf1_write_config32(dev, 0x4c, dword);
|
||||
pci_write_config32(dev, 0x4c, dword);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
|
@ -84,7 +84,7 @@ static void pci_init(struct device *dev)
|
|||
printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
|
||||
#endif
|
||||
printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
|
||||
pci_conf1_write_config32(dev, 0x50, dword); //TOM
|
||||
pci_write_config32(dev, 0x50, dword); //TOM
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -39,10 +39,10 @@ static void pcie_init(struct device *dev)
|
|||
u32 dword;
|
||||
|
||||
/* System error enable */
|
||||
dword = pci_conf1_read_config32(dev, 0x04);
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
dword |= (1<<8); /* System error enable */
|
||||
dword |= (1<<30); /* Clear possible errors */
|
||||
pci_conf1_write_config32(dev, 0x04, dword);
|
||||
pci_write_config32(dev, 0x04, dword);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static void sata_init(struct device *dev)
|
|||
struct southbridge_nvidia_mcp55_sata_config *conf =
|
||||
(struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration;
|
||||
|
||||
dword = pci_conf1_read_config32(dev, 0x50);
|
||||
dword = pci_read_config32(dev, 0x50);
|
||||
/* Ensure prefetch is disabled */
|
||||
dword &= ~((1 << 15) | (1 << 13));
|
||||
if(conf) {
|
||||
|
|
@ -62,11 +62,11 @@ static void sata_init(struct device *dev)
|
|||
dword &= ~(0x1f<<24);
|
||||
dword |= (0x15<<24);
|
||||
#endif
|
||||
pci_conf1_write_config32(dev, 0x50, dword);
|
||||
pci_write_config32(dev, 0x50, dword);
|
||||
|
||||
dword = pci_conf1_read_config32(dev, 0xf8);
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 2;
|
||||
pci_conf1_write_config32(dev, 0xf8, dword);
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
}
|
||||
|
||||
struct device_operations mcp55_sata = {
|
||||
|
|
|
|||
|
|
@ -41,9 +41,9 @@
|
|||
static void usb2_init(struct device *dev)
|
||||
{
|
||||
u32 dword;
|
||||
dword = pci_conf1_read_config32(dev, 0xf8);
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 40;
|
||||
pci_conf1_write_config32(dev, 0xf8, dword);
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
}
|
||||
|
||||
static void usb2_set_resources(struct device *dev)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue