diff --git a/arch/x86/amd/model_fxx/init_cpus.c b/arch/x86/amd/model_fxx/init_cpus.c index 6edd39d383..12729244b8 100644 --- a/arch/x86/amd/model_fxx/init_cpus.c +++ b/arch/x86/amd/model_fxx/init_cpus.c @@ -300,9 +300,9 @@ void STOP_CAR_AND_CPU(void) #if MEM_TRAIN_SEQ == 1 -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, +void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, - unsigned retcall); + void * retcall); #endif /** @@ -479,7 +479,7 @@ cpu_init_detectedx = 0; /* this is not done on Serengeti. */ #if MEM_TRAIN_SEQ == 1 train_ram_on_node(id.nodeid, id.coreid, sysinfo, - STOP_CAR_AND_CPU); + (void *)STOP_CAR_AND_CPU); #endif /* this is inline and there is no return. */ STOP_CAR_AND_CPU(); diff --git a/mainboard/gigabyte/m57sli/mainboard.h b/mainboard/gigabyte/m57sli/mainboard.h index 5a57d5a799..f0c745e9cd 100644 --- a/mainboard/gigabyte/m57sli/mainboard.h +++ b/mainboard/gigabyte/m57sli/mainboard.h @@ -43,3 +43,6 @@ /* architecture stuff which ought to be set "somewhere" "SOMEHOW" */ /* preferably by asking the CPU, not be a DEFINE! */ #define CPU_ADDR_BITS 40 + +/* you don't want to set this in Kconfig or dts either. It's dangerous! */ +#define CONFIG_AP_CODE_IN_CAR 0 diff --git a/northbridge/amd/k8/dqs.c b/northbridge/amd/k8/dqs.c index 51c6c75aea..67912b1f96 100644 --- a/northbridge/amd/k8/dqs.c +++ b/northbridge/amd/k8/dqs.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1938,10 +1939,11 @@ out: #if MEM_TRAIN_SEQ > 0 -static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned int v) +void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int ii; + int v = 1; /* used to be a parameter; consider making it one again */ u64 tsc[4]; @@ -1972,9 +1974,8 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } tsc[1] = cycles(); if (DQS_TRAIN_DEBUG) { - printk(BIOS_DEBUG, "set DQS timing:DQSPos: "); + printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x", i); } - print_debug_hex8(i); } if(train_DqsPos(ctrl, sysinfo)) { @@ -1987,9 +1988,8 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info tsc[2] = cycles(); if (DQS_TRAIN_DEBUG) { - printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: "); + printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i); } - print_debug_hex8(i); } if(train_DqsRcvrEn(ctrl, 2, sysinfo)){ sysinfo->mem_trained[i]=0x83; // @@ -2011,7 +2011,7 @@ out: if(v) { for(ii=0;ii<4;ii++) { - print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); + printk(BIOS_ERR, "Total DQS Training : tsc %d: %llx", ii, tsc[ii]); } } @@ -2025,17 +2025,21 @@ out: #if MEM_TRAIN_SEQ == 1 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { - dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy + dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo); // keep the output tidy // memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); // memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; } static void copy_and_run_ap_code_in_car(unsigned ret_addr); -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) +void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, void * retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + /* this is a little weird. We're going to get the address of the global vars. But we're in CAR, so + * it's really private. We're going to copy from global memory, which is node 0 memory, which + * is working at this point. + */ + struct sys_info *sysinfox = & global_vars()->sys_info; wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { @@ -2046,7 +2050,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else - memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE); + memcpy(sysinfo, sysinfox, sizeof(*sysinfo)); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 @@ -2056,7 +2060,9 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy #else /* Can copy dqs_timing to ap cache and run from cache? * we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom for ap ? + * not sure how we'll return. */ +#warning resolve issues about returning from the copy_and_run_ap_code_in_car. copy_and_run_ap_code_in_car(retcall); // will go back by jump #endif diff --git a/northbridge/amd/k8/raminit.c b/northbridge/amd/k8/raminit.c index 93b958a8ed..d5e2f76922 100644 --- a/northbridge/amd/k8/raminit.c +++ b/northbridge/amd/k8/raminit.c @@ -2653,10 +2653,10 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some - u32 basek_pri; + u32 basek_pri = 0; for(i=0; iide1_enable) { @@ -56,15 +56,15 @@ static void ide_init(struct device *dev) word |= (1<<12); word |= (1<<14); - pci_conf1_write_config16(dev, 0x50, word); + pci_write_config16(dev, 0x50, word); byte = 0x20 ; // Latency: 64-->32 - pci_conf1_write_config8(dev, 0xd, byte); + pci_write_config8(dev, 0xd, byte); - dword = pci_conf1_read_config32(dev, 0xf8); + dword = pci_read_config32(dev, 0xf8); dword |= 12; - pci_conf1_write_config32(dev, 0xf8, dword); + pci_write_config32(dev, 0xf8, dword); #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif diff --git a/southbridge/nvidia/mcp55/lpc.c b/southbridge/nvidia/mcp55/lpc.c index 130bc549f9..1d0c9b46ef 100644 --- a/southbridge/nvidia/mcp55/lpc.c +++ b/southbridge/nvidia/mcp55/lpc.c @@ -144,10 +144,10 @@ static void lpc_common_init(struct device *dev, int master) u32 dword; /* IO APIC initialization */ - byte = pci_conf1_read_config8(dev, 0x74); + byte = pci_read_config8(dev, 0x74); byte |= (1<<0); // enable APIC - pci_conf1_write_config8(dev, 0x74, byte); - dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + pci_write_config8(dev, 0x74, byte); + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 setup_ioapic(dword, master); } @@ -162,8 +162,8 @@ static void enable_hpet(struct device *dev) { unsigned long hpet_address; - pci_conf1_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe; + pci_write_config32(dev,0x44, 0xfed00001); + hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); } #endif @@ -180,20 +180,20 @@ static void lpc_init(struct device *dev) #warning posted memory write enable disabled in mcp55 lpc? #if 0 /* posted memory write enable */ - byte = pci_conf1_read_config8(dev, 0x46); - pci_conf1_write_config8(dev, 0x46, byte | (1<<0)); + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1<<0)); #endif /* power after power fail */ #if 1 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); - byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { byte |= 0x40; } - pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte); + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); #endif /* Throttle the CPU speed down for testing */ @@ -202,7 +202,7 @@ static void lpc_init(struct device *dev) if(on) { u16 pm10_bar; u32 dword; - pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00); + pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; @@ -213,16 +213,16 @@ static void lpc_init(struct device *dev) #if 0 // default is enabled /* Enable Port 92 fast reset */ - byte = pci_conf1_read_config8(dev, 0xe8); + byte = pci_read_config8(dev, 0xe8); byte |= ~(1 << 3); - pci_conf1_write_config8(dev, 0xe8, byte); + pci_write_config8(dev, 0xe8, byte); #endif /* Enable Error reporting */ /* Set up sync flood detected */ - byte = pci_conf1_read_config8(dev, 0x47); + byte = pci_read_config8(dev, 0x47); byte |= (1 << 1); - pci_conf1_write_config8(dev, 0x47, byte); + pci_write_config8(dev, 0x47, byte); /* Set up NMI on errors */ byte = inb(0x70); // RTC70 @@ -286,7 +286,7 @@ static void mcp55_lpc_enable_childrens_resources(struct device *dev) int i; int var_num = 0; - reg = pci_conf1_read_config32(dev, 0xa0); + reg = pci_read_config32(dev, 0xa0); for (link = 0; link < dev->links; link++) { struct device *child; @@ -324,9 +324,9 @@ static void mcp55_lpc_enable_childrens_resources(struct device *dev) } } } - pci_conf1_write_config32(dev, 0xa0, reg); + pci_write_config32(dev, 0xa0, reg); for(i=0;iid.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) ) ) { u32 id; - id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID); + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) || (id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))) ) { @@ -82,7 +82,7 @@ static void mcp55_enable(struct device *dev) /* sorry. Again, anonymous unions etc. would make this easier. */ if(dev->id.pci.device==0x0000) { - vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID); + vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; // vendorid &= 0xffff; } else { @@ -180,14 +180,14 @@ static void mcp55_enable(struct device *dev) if(!sm_dev) return; if ( sm_dev ) { - reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4); + reg_old = reg = pci_read_config32(sm_dev, 0xe4); if (!dev->enabled) { //disable it reg |= (1<bus->secondary, devfn + 1); if(!sm_dev) return; - final_reg = pci_conf1_read_config32(sm_dev, 0xe8); + final_reg = pci_read_config32(sm_dev, 0xe8); final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9)); - pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all at first + pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first #if 0 - reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4); + reg_old = reg = pci_read_config32(sm_dev, 0xe4); // reg |= (1<<0); reg &= ~(0x3f<<4); if (reg != reg_old) { printk_debug("mcp55.c pcie enabled\n"); - pci_conf1_write_config32(sm_dev, 0xe4, reg); + pci_write_config32(sm_dev, 0xe4, reg); } #endif } @@ -238,9 +238,9 @@ static void mcp55_enable(struct device *dev) if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); if(!sm_dev) return; - reg_old = pci_conf1_read_config32(sm_dev, 0xe8); + reg_old = pci_read_config32(sm_dev, 0xe8); if (final_reg != reg_old) { - pci_conf1_write_config32(sm_dev, 0xe8, final_reg); + pci_write_config32(sm_dev, 0xe8, final_reg); } } @@ -251,7 +251,7 @@ static void mcp55_enable(struct device *dev) void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { - pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/southbridge/nvidia/mcp55/pci.c b/southbridge/nvidia/mcp55/pci.c index 5dad0b0320..df61516616 100644 --- a/southbridge/nvidia/mcp55/pci.c +++ b/southbridge/nvidia/mcp55/pci.c @@ -43,23 +43,23 @@ static void pci_init(struct device *dev) #endif /* System error enable */ - dword = pci_conf1_read_config32(dev, 0x04); + dword = pci_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ dword |= (1<<30); /* Clear possible errors */ - pci_conf1_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword); #if 1 //only need (a01,xx] - word = pci_conf1_read_config16(dev, 0x48); + word = pci_read_config16(dev, 0x48); word |= (1<<0); /* MRL2MRM */ word |= (1<<2); /* MR2MRM */ - pci_conf1_write_config16(dev, 0x48, word); + pci_write_config16(dev, 0x48, word); #endif #if 1 - dword = pci_conf1_read_config32(dev, 0x4c); + dword = pci_read_config32(dev, 0x4c); dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ - pci_conf1_write_config32(dev, 0x4c, dword); + pci_write_config32(dev, 0x4c, dword); #endif #ifdef CONFIG_PCI_64BIT_PREF_MEM @@ -84,7 +84,7 @@ static void pci_init(struct device *dev) printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); #endif printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_conf1_write_config32(dev, 0x50, dword); //TOM + pci_write_config32(dev, 0x50, dword); //TOM } diff --git a/southbridge/nvidia/mcp55/pcie.c b/southbridge/nvidia/mcp55/pcie.c index 6ccef8c626..5b5a2c3a48 100644 --- a/southbridge/nvidia/mcp55/pcie.c +++ b/southbridge/nvidia/mcp55/pcie.c @@ -39,10 +39,10 @@ static void pcie_init(struct device *dev) u32 dword; /* System error enable */ - dword = pci_conf1_read_config32(dev, 0x04); + dword = pci_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ dword |= (1<<30); /* Clear possible errors */ - pci_conf1_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword); } diff --git a/southbridge/nvidia/mcp55/sata.c b/southbridge/nvidia/mcp55/sata.c index 6ad51f430f..1df2169ed9 100644 --- a/southbridge/nvidia/mcp55/sata.c +++ b/southbridge/nvidia/mcp55/sata.c @@ -40,7 +40,7 @@ static void sata_init(struct device *dev) struct southbridge_nvidia_mcp55_sata_config *conf = (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration; - dword = pci_conf1_read_config32(dev, 0x50); + dword = pci_read_config32(dev, 0x50); /* Ensure prefetch is disabled */ dword &= ~((1 << 15) | (1 << 13)); if(conf) { @@ -62,11 +62,11 @@ static void sata_init(struct device *dev) dword &= ~(0x1f<<24); dword |= (0x15<<24); #endif - pci_conf1_write_config32(dev, 0x50, dword); + pci_write_config32(dev, 0x50, dword); - dword = pci_conf1_read_config32(dev, 0xf8); + dword = pci_read_config32(dev, 0xf8); dword |= 2; - pci_conf1_write_config32(dev, 0xf8, dword); + pci_write_config32(dev, 0xf8, dword); } struct device_operations mcp55_sata = { diff --git a/southbridge/nvidia/mcp55/usb2.c b/southbridge/nvidia/mcp55/usb2.c index c3c4b106b2..6ba3c103e7 100644 --- a/southbridge/nvidia/mcp55/usb2.c +++ b/southbridge/nvidia/mcp55/usb2.c @@ -41,9 +41,9 @@ static void usb2_init(struct device *dev) { u32 dword; - dword = pci_conf1_read_config32(dev, 0xf8); + dword = pci_read_config32(dev, 0xf8); dword |= 40; - pci_conf1_write_config32(dev, 0xf8, dword); + pci_write_config32(dev, 0xf8, dword); } static void usb2_set_resources(struct device *dev)