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soc/intel/common/fast_spi: support caching bios in ramstage
After the MTRR solution has been calculated provide a way for code to call the same function, fast_spi_cache_bios_region(), in all stages. This is accomplished by using the ramstage temporary MTRR support. Change-Id: I84ec90be3a1b0d6ce84d9d8e12adc18148f8fcfb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20115 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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2 changed files with 17 additions and 8 deletions
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@ -179,14 +179,10 @@ size_t fast_spi_get_bios_region(size_t *bios_size)
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void fast_spi_cache_bios_region(void)
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void fast_spi_cache_bios_region(void)
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{
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{
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int mtrr;
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size_t bios_size;
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size_t bios_size;
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uint32_t alignment;
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uint32_t alignment;
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const int type = MTRR_TYPE_WRPROT;
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mtrr = get_free_var_mtrr();
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uintptr_t base;
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if (mtrr == -1)
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return;
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/* Only the IFD BIOS region is memory mapped (at top of 4G) */
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/* Only the IFD BIOS region is memory mapped (at top of 4G) */
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fast_spi_get_bios_region(&bios_size);
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fast_spi_get_bios_region(&bios_size);
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@ -197,7 +193,18 @@ void fast_spi_cache_bios_region(void)
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/* Round to power of two */
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/* Round to power of two */
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alignment = 1 << (log2_ceil(bios_size));
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alignment = 1 << (log2_ceil(bios_size));
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bios_size = ALIGN_UP(bios_size, alignment);
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bios_size = ALIGN_UP(bios_size, alignment);
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set_var_mtrr(mtrr, 4ULL*GiB - bios_size, bios_size, MTRR_TYPE_WRPROT);
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base = 4ULL*GiB - bios_size;
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if (ENV_RAMSTAGE) {
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mtrr_use_temp_range(base, bios_size, type);
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} else {
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int mtrr = get_free_var_mtrr();
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if (mtrr == -1)
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return;
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set_var_mtrr(mtrr, base, bios_size, type);
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}
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}
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}
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/*
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/*
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@ -57,7 +57,9 @@ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data);
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*/
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*/
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size_t fast_spi_get_bios_region(size_t *bios_size);
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size_t fast_spi_get_bios_region(size_t *bios_size);
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/*
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/*
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* Cache the memory-mapped BIOS region as write-protect type.
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* Cache the memory-mapped BIOS region as write-protect type. In ramstage
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* this function needs to be called after the final MTRR solution has been
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* calculated.
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*/
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*/
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void fast_spi_cache_bios_region(void);
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void fast_spi_cache_bios_region(void);
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/*
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/*
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